1Gb DDR3L – AS4C128M8D3L
Timing of RD/RDA command to Power
Down entry
RL + 4 +
tRDPDEN
tWRPDEN
-
-
tCK
tCK
1
WL + 4
+
(tWR / tCK)
WL + 4
+ WR +
1
WL + 2
+
(tWR / tCK)
WL + 2
+ WR +
1
Timing of WR command to Power Down
entry (BL8OTF, BL8MRS, BC4OTF)
9
10
9
Timing of WRA command to Power
Down entry (BL8OTF, BL8MRS,BC4OTF)
tWRAPDEN
-
-
-
tCK
Timing of WR command to Power Down entry
(BC4MRS)
tWRPDEN
tCK
Timing of WRA command to Power Down entry
(BC4MRS)
tWRAPDEN
tREFPDEN
tCK
tCK
10
20,
21
Timing of REF command to Power Down entry
1
-
tMOD(min)
-
tMRSPDEN Timing of MRS command to Power Down entry
ODT turn on Latency
WL - 2 = CWL + AL - 2
WL - 2 = CWL + AL - 2
ODTLon
tCK
ODT turn off Latency
ODTLoff
ODT high time without write command or
with write command and BC4
ODT high time with Write command and BL8
Asynchronous RTT turn-on delay (Power- Down
4
6
2
-
-
tCK
tCK
ns
ODTH4
ODTH8
tAONPD
8.5
with DLL frozen)
Asynchronous RTT turn-off delay (Power-
Down with DLL frozen)
RTT turn-on
RTT_Nom and RTT_WR turn-off time
from ODTLoff reference
RTT dynamic change skew
First DQS/DQS# rising edge after write
leveling mode is programmed
tAOFPD
2
8.5
225
0.7
0.7
-
ns
ps
tCK
tCK
tCK
tAON
-225
0.3
0.3
40
7
8
tAOF
tADC
tWLMRD
3
3
DQS/DQS# delay after write leveling
mode is programmed
Write leveling setup time from rising CK,
CK# crossing to rising DQS, DQS# crossing
Write leveling hold time from rising DQS,
DQS# crossing to rising CK, CK# crossing
tWLDQSEN
tWLS
25
-
-
-
tCK
ps
ps
165
165
tWLH
tWLO
tWLOE
tRFC
Write leveling output delay
0
0
7.5
2
ns
ns
ns
μs
μs
Write leveling output error
REF command to ACT or REF command time
110
-
-
-40°C to 85°C
85°C to 95°C
7.8
3.9
tREFI
Average periodic refresh interval
-
NOTE 1: Actual value dependant upon measurement level.
NOTE 2: Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands.
NOTE 3: The max values are system dependent.
NOTE 4: WR as programmed in mode register.
NOTE 5: Value must be rounded-up to next higher integer value
NOTE 6: There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.
NOTE 7: For definition of RTT turn-on time tAON See “Timing Parameters”.
NOTE 8: For definition of RTT turn-off time tAOF See “Timing Parameters”.
NOTE 9: tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer.
NOTE 10: WR in clock cycles as programmed in MR0.
NOTE 11: The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on
the right side. See “Clock to Data Strobe Relationship”.
Confidential
28
Rev. 2.0
Aug. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
