1Gb DDR3L – AS4C128M8D3L
max
Internal READ Command to
PRECHARGE Command delay
tRTP
(4tCK,
7.5ns)
max
(4tCK,
7.5ns)
-
-
tCK
Delay from start of internal write
transaction to internal read command
tWTR
tCK
18
18
tWR
WRITE recovery time
15
4
-
-
ns
tMRD
Mode Register Set command cycle time
tCK
max
12tCK,
15ns)
tMOD
Mode Register Set command update delay
-
tCK
tCCD
CAS# to CAS# command delay
4
-
tCK
tCK
tCK
tDAL(min)
tMPRR
Auto precharge write recovery + prechargetime
Multi-Purpose Register Recovery Time
WR + tRP
1
-
22
16
max
(4tCK,
6ns)
30
60
tRRD
ACTIVE to ACTIVE command period
Four activate window
-
tCK
tFAW
-
-
-
ns
ps
AC160
Command and Address setup time to CK,
CK# referenced to Vih(ac) / Vil(ac) levels
tIS(base)
AC135
185
ps 16,27
Command and Address hold time from CK,
CK# referenced to Vih(dc) / Vil(dc) levels
Control and Address Input pulse width for each
input
tIH(base)
tIPW
DC90
130
560
-
-
ps
ps
16
28
tZQinit
tZQoper
tZQCS
Power-up and RESET calibration time
Normal operation Full calibration time
Normal operation Short calibration time
512
256
64
-
-
-
tCK
tCK
tCK
23
max(5tCK,
tXPR
Exit Reset from CKE HIGH to a valid command
tRFC(min)
10ns)
max(5tCK,
tRFC(min)
10ns)
+
-
-
tCK
Exit Self Refresh to commands not
requiring a locked DLL
tXS
+
tCK
Exit Self Refresh to commands requiring a
locked DLL
Minimum CKE low width for Self Refresh
entry to exit timing
tXSDLL
tCKESR
tCKSRE
tCKSRX
tDLLK(min)
-
-
-
-
tCK
tCK
tCK
tCK
tCKE(min)
+ 1tCK
Valid Clock Requirement after Self Refresh Entry max(5tCK,
10 ns)
Valid Clock Requirement before Self Refresh Exit max(5tCK,
(SRE) or Power-Down Entry (PDE)
10 ns)
(SRX) or Power-Down Exit (PDX) or Reset Exit
Exit Power Down with DLL on to any valid
command; Exit Precharge Power Down with DLL
frozen to commands not requiring a locked DLL
max(3tCK,
6 ns)
tXP
-
tCK
max
(10tCK,
24 ns)
max(3tCK,
5 ns)
Exit Precharge Power Down with DLL
frozen to commands requiring a lockedDLL
tXPDLL
-
-
tCK
2
tCKE
tCPDED
tPD
tACTPDEN
CKE minimum pulse width
tCK
tCK
Command pass disable delay
2
-
Power Down Entry to Exit Timing
Timing of ACT command to Power Down
entry
Timing of PRE or PREA command to
Power Down entry
tCKE(min)
9 * tREFI
15
20
1
1
-
-
tCK
tCK
tPRPDEN
20
Confidential
27
Rev. 2.0
Aug. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
