1Gb DDR3L – AS4C128M8D3L
Table 18. Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 1.35V)
-12
Symbol
Parameter
Unit Note
Min.
13.75
13.75
13.75
48.75
35
Max.
20
tAA
Internal read command to first data
ACT to internal read or write delay time
PRE command period
ns
ns
ns
ns
ns
ns
ns
tRCD
tRP
-
-
tRC
ACT to ACT or REF command period
ACTIVE to PRECHARGE command period
-
tRAS
9 * tREFI
<3.3
<3.3
<2.5
<2.5
<1.875
<1.875
<1. 5
-
CL=5, CWL=5
3.0
CL=6, CWL=5
2.5
CL=7, CWL=6
CL=8, CWL=6
CL=9, CWL=7
CL=10, CWL=7
CL=11, CWL=8
1.875
1.875
1.5
ns
ns
ns
ns
ns
ns
tCK
tCK
ps
tCK
33
33
33
33
33
6
tCK(avg)
Average clock period
1.5
1.25
8
tCK
Minimum Clock Cycle Time (DLL off mode)
Average clock HIGH pulse width
(DLL_OFF)
tCH(avg)
tCL(avg)
tDQSQ
0.47
0.47
-
0.53
0.53
100
-
Average Clock LOW pulse width
DQS, DQS# to DQ skew, per group, per access
DQ output hold time from DQS, DQS#
DQ low-impedance time from CK, CK#
DQ high impedance time from CK, CK#
13
13
tQH
0.38
-450
-
tLZ(DQ)
tHZ(DQ)
225
225
ps 13,14
ps 13,14
Data setup time to DQS, DQS#
AC135
tDS(base)
tDH(base)
25
55
-
-
ps
17
17
referenced to Vih(ac) / Vil(ac) levels
Data hold time from DQS, DQS#
DC90
ps
ps
referenced to Vih(dc) / Vil(dc) levels
tDIPW
tRPRE
tRPST
tQSH
DQ and DM Input pulse width for each input
DQS,DQS# differential READ Preamble
DQS, DQS# differential READ Postamble
DQS, DQS# differential output high time
DQS, DQS# differential output low time
DQS, DQS# differential WRITE Preamble
DQS, DQS# differential WRITE Postamble
360
0.9
0.3
0.4
0.4
0.9
0.3
-
-
-
-
-
-
-
tCK 13,19
tCK 11,13
tCK
tCK
tCK
tCK
13
13
1
tQSL
tWPRE
tWPST
1
DQS, DQS# rising edge output access
time from rising CK, CK#
DQS and DQS# low-impedance time
(Referenced from RL - 1)
tDQSCK
tLZ(DQS)
tHZ(DQS)
tDQSL
-225
-450
-
225
225
225
0.55
ps
ps
ps
tCK
13
13,
14
DQS and DQS# high-impedance time
(Referenced from RL + BL/2)
13,
14
29,
31
DQS, DQS# differential input low pulse width
0.45
30,
31
tDQSH
tDQSS
tDSS
DQS, DQS# differential input high pulse width
DQS, DQS# rising edge to CK, CK# rising edge
DQS, DQS# falling edge setup time to
CK, CK# rising edge
DQS, DQS# falling edge hold time from
CK, CK# rising edge
DLL locking time
0.45
-0.27
0.18
0.55
0.27
-
tCK
tCK
tCK
32
32
tDSH
0.18
512
-
-
tCK
tCK
tDLLK
Confidential
26
Rev. 2.0
Aug. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
