2Gb DDR3L – AS4C128M16D3L
max
(4nCK,
7.5ns)
Delay from start of internal write
transaction to internal read command
tWTR
-
WRITE recovery time
tWR
15
4
-
-
ns
Mode Register Set command cycle time
tMRD
tCK
max
(12nCK,
15ns)
Mode Register Set command update delay
tMOD
-
-
CAS# to CAS# command delay
tCCD
4
tCK
tCK
tCK
Auto precharge write recovery + prechargetime
Multi-Purpose Register Recovery Time
tDAL(min)
tMPRR
WR + tRP
1
-
max
(4nCK,
7.5ns)
-
ACTIVE to ACTIVE command period
tRRD
Four activate window
tFAW
40
60
-
-
-
ns
ps
ps
AC160
Command and Address setup time to CK,
CK# referenced to Vih(ac) / Vil(ac) levels
tIS(base)
AC135
DC90
185
Command and Address hold time from CK,
CK# referenced to Vih(dc) / Vil(dc) levels
Control and Address Input pulse width for
each input
tIH(base)
tIPW
130
560
-
-
ps
-
Power-up and RESET calibration time
Normal operation Full calibration time
Normal operation Short calibration time
tZQinit
tZQoper
tZQCS
512
256
-
-
-
tCK
tCK
tCK
64
max(5nCK,
tRFC+10ns)
max(5nCK,
tRFC+10ns)
-
-
-
-
Exit Reset from CKE HIGH to a valid command
tXPR
Exit Self Refresh to commands not
requiring a locked DLL
Exit Self Refresh to commands requiring a
locked DLL
Minimum CKE low width for Self Refresh
entry to exit timing
tXS
tXSDLL
tCKESR
tDLLK(min)
tCK
tCKE(min)
+1nCK
max
(5nCK,
10 ns)
max
(5nCK,
10 ns)
max
(3nCK,
6 ns)
Valid Clock Requirement after Self Refresh Entry (SRE)
or Power-Down Entry (PDE)
-
-
-
-
-
tCKSRE
tCKSRX
tXP
Valid Clock Requirement before Self Refresh Exit
(SRX) or Power-Down Exit (PDX) or Reset Exit
Exit Power Down with DLL on to any valid command;
Exit Precharge Power Down with DLL frozen to
commands not requiring a locked DLL
max
Exit Precharge Power Down with DLL
frozen to commands requiring a lockedDLL
tXPDLL
(10nCK,
24 ns)
max
(3nCK,
5ns)
CKE minimum pulse width
tCKE
Command pass disable delay
tCPDED
tPD
1
tCKE(min)
1
-
tCK
Power Down Entry to Exit Timing
9 * tREFI
-
Timing of ACT command to Power Down entry
tACTPDEN
tCK
tCK
tCK
tCK
Timing of PRE or PREA command to
Power Down entry
tPRPDEN
tRDPDEN
tWRPDEN
1
-
-
Timing of RD/RDA command to Power Down entry
RL + 4 + 1
WL + 4
+(tWR / tCK)
Timing of WR command to Power Down
entry (BL8OTF, BL8MRS, BC4OTF)
-
Confidential
27
Rev. 2.0
Aug. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
