2Gb DDR3L – AS4C128M16D3L
Burst Refresh Current
CKE: High; External clock: On; BL: 8*1; AL: 0; CS#: High between tREF;
Command, Address, Bank Address Inputs: partially toggling; Data IO: MID-
LEVEL;DM:stable at 0; Bank Activity: REF command every tRFC; Output
Buffer and RTT: Enabled in Mode Registers*2; ODT Signal: stable at 0.
Self Refresh Current:
IDD5B
135
mA
Auto Self-Refresh (ASR): Disabled*4; Self-Refresh
TCASE: 0 - 85°C
IDD6
11
14
mA
mA
Temperature Range (SRT): Normal*5; CKE: Low;
External clock: Off; CK and CK#: LOW; BL: 8*1; AL: 0;
CS#, Command, Address, Bank Address, Data IO: MID-
LEVEL;DM:stable at 0; Bank Activity: Self-Refresh
TCASE: -40 - 95°C
IDD6ET
operation; Output Buffer and RTT: Enabled in Mode
Registers*2; ODT Signal: MID-LEVEL
Operating Bank Interleave Read Current:
CKE: High; External clock: On; BL: 8*1, 7; AL: CL-1; CS#: High between ACT
and RDA; Command, Address, Bank Address Inputs: partially toggling;
DM:stable at 0; Output Buffer and RTT: Enabled in Mode Registers*2; ODT
Signal: stable at 0.
IDD7
210
13
mA
mA
RESET Low Current:
RESET: Low; External clock: Off; CK and CK# : Low ; CKE : Floating ; CS,
Command, Address, Bank Address, Data IO : Floating ; ODT Signal :
Floating
IDD8
NOTE 1. Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
NOTE 2. Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B;
RTT_Wr enable: set MR2 A[10,9] = 10B
NOTE 3. Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit
NOTE 4. Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
NOTE 5. Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range
NOTE 6. Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are
supported by DDR3L SDRAM device
NOTE 7. Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B
Confidential
25
Rev. 2.0
Aug. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
