2Gb DDR3L – AS4C128M16D3L
Table 18. Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 1.35V)
-12
Symbol
Parameter
Unit
Min.
13.75
13.75
13.75
48.75
35
Max.
20
Internal read command to first data
ACT to internal read or write delay time
PRE command period
tAA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ps
tCK
ps
ps
tRCD
tRP
-
-
ACT to ACT or REF command period
ACTIVE to PRECHARGE command period
tRC
-
tRAS
9 * tREFI
<3.3
<3.3
<2.5
<2.5
<1.875
<1.875
<1.5
-
CL=5, CWL=5
3.0
CL=6, CWL=5
CL=7, CWL=6
CL=8, CWL=6
CL=9, CWL=7
CL=10, CWL=7
CL=11, CWL=8
2.5
1.875
1.875
1.5
Average clock period
tCK(avg)
1.5
1.25
8
Minimum Clock Cycle Time (DLL off mode)
Average clock HIGH pulse width
tCK
(DLL_OFF)
tCH(avg)
tCL(avg)
tDQSQ
0.47
0.47
-
0.53
0.53
100
-
Average Clock LOW pulse width
DQS, DQS# to DQ skew, per group, per access
DQ output hold time from DQS, DQS#
DQ low-impedance time from CK, CK#
DQ high impedance time from CK, CK#
Data setup time to DQS, DQS#
tQH
0.38
-450
-
tLZ(DQ)
tHZ(DQ)
tDS(base)
225
225
AC135
25
55
-
-
ps
ps
referenced to Vih(ac) / Vil(ac) levels
Data hold time from DQS, DQS#
referenced to Vih(dc) / Vil(dc) levels
DQ and DM Input pulse width for each input
tDH(base)
DC90
tDIPW
tRPRE
tRPST
tQSH
360
0.9
0.3
0.4
0.4
0.9
0.3
-
-
-
-
-
-
-
ps
tCK
tCK
tCK
tCK
tCK
tCK
DQS,DQS# differential READ Preamble
DQS, DQS# differential READ Postamble
DQS, DQS# differential output high time
DQS, DQS# differential output low time
DQS, DQS# differential WRITE Preamble
DQS, DQS# differential WRITE Postamble
tQSL
tWPRE
tWPST
DQS, DQS# rising edge output access
time from rising CK, CK#
DQS and DQS# low-impedance time
(Referenced from RL - 1)
DQS and DQS# high-impedance time
(Referenced from RL + BL/2)
tDQSCK
tLZ(DQS)
tHZ(DQS)
-225
-450
-
225
225
225
ps
ps
ps
DQS, DQS# differential input low pulse width
DQS, DQS# differential input high pulse width
DQS, DQS# rising edge to CK, CK# rising edge
tDQSL
tDQSH
tDQSS
0.45
0.45
-0.27
0.55
0.55
0.27
tCK
tCK
tCK
DQS, DQS# falling edge setup time to
CK, CK# rising edge
tDSS
0.18
-
tCK
DQS, DQS# falling edge hold time from
CK, CK# rising edge
tDSH
0.18
512
-
-
tCK
tCK
DLL locking time
tDLLK
max
(4nCK,
7.5ns)
Internal READ Command to
PRECHARGE Command delay
-
tRTP
Confidential
26
Rev. 2.0
Aug. /2014
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
