AS4C128M16D3A-12BIN
z Jitter Notes
NOTE 1. Unit ‘tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ‘nCK’ represents
one clock cycle of the input clock, counting the actual clock edges.ex) tMRD = 4 [nCK] means; if one
Mode Register Set command is registered at Tm, another Mode Register Set command may be
registered at Tm+4, even if (Tm+4 - Tm) is 4 x tCK(avg) + tERR(4per),min.
NOTE 2. These parameters are measured from a command/address signal (CKE, CS#, RAS#, CAS#, WE#,
ODT, BA0, A0, A1, etc.) transition edge to its respective clock signal (CK/CK#) crossing. The spec
values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup
and hold are relative to the clock signal crossing that latches the command/address. That is, these
parameters should be met whether clock jitter is present or not.
NOTE 3. These parameters are measured from a data strobe signal (DQS(L/U), DQS(L/U)#) crossing to its
respective clock signal (CK, CK#) crossing. The spec values are not affected by the amount of clock
jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the clock signal crossing. That is,
these parameters should be met whether clock jitter is present or not.
NOTE 4. These parameters are measured from a data signal (DM(L/U), DQ(L/U)0, DQ(L/U)1, etc.) transition
edge to its respective data strobe signal (DQS(L/U), DQS(L/U)#) crossing.
NOTE 5. For these parameters, the DDR3 SDRAM device supports tnPARAM [nCK] = RU{ tPARAM [ns] /
tCK(avg) [ns] }, which is in clock cycles, assuming all input clock jitter specifications are satisfied.
NOTE 6. When the device is operated with input clock jitter, this parameter needs to be derated by the actual
tERR(mper),act of the input clock, where 2 <= m <= 12. (output deratings are relative to the SDRAM
input clock.)
NOTE 7. When the device is operated with input clock jitter, this parameter needs to be derated by the actual
tJIT(per),act of the input clock. (output deratings are relative to the SDRAM input clock.)
Table 21. Input clock jitter spec parameter
-12
Parameter
Symbol
tJIT (per)
Unit
Max.
70
Min.
Clock period jitter
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
-70
Clock period jitter during DLL locking period
Cycle to cycle clock period jitter
tJIT (per,lck)
tJIT (cc)
60
-60
140
120
Cycle to cycle clock period jitter during DLL locking period
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across 6 cycles
Cumulative error across 7 cycles
Cumulative error across 8 cycles
Cumulative error across 9 cycles
Cumulative error across 10 cycles
Cumulative error across 11 cycles
Cumulative error across 12 cycles
tJIT (cc,lck)
tERR (2per)
tERR (3per)
tERR (4per)
tERR (5per)
tERR (6per)
tERR (7per)
tERR (8per)
tERR (9per)
tERR (10per)
tERR (11per)
tERR (12per)
103
122
136
147
155
163
169
175
180
184
188
-103
-122
-136
-147
-155
-163
-169
-175
-180
-184
-188
t
ERR (nper)min = (1+0.68ln(n)) * tJIT (per)min
Cumulative error across n cycles, n=13...50, inclusive
tERR (nper)
ps
tERR (nper)max = (1+0.68ln(n)) * tJIT (per)max
Confidential
-34／83-
Rev. 1.0 May 2016
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
