AS4C128M16D3A-12BIN
Table 18. Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 1.5V ± 0.075V, TOPER = -40~95 °C)
-12
Symbol
Parameter
Unit
Min.
13.75
13.75
Max.
20
Internal read command to first data
ACT to internal read or write delay time
PRE command period
tAA
ns
ns
ns
ns
-
-
-
tRCD
tRP
13.75
48.75
ACT to ACT or REF command period
tRC
9 *
tREFI
ACTIVE to PRECHARGE command period
tRAS
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ps
tCK
ps
ps
ps
3.3
3.3
CL=5, CWL=5
3.0
2.5
CL=6, CWL=5
CL=7, CWL=6
CL=8, CWL=6
CL=9, CWL=7
CL=10, CWL=7
CL=11, CWL=8
<2.5
1.875
1.875
1.5
Average clock period
tCK(avg)
<2.5
<1.875
<1.875
<1.5
-
1.5
1.25
8
Minimum Clock Cycle Time (DLL off mode)
Average clock HIGH pulse width
tCK
(DLL_OFF)
0.53
0.53
100
-
tCH(avg)
tCL(avg)
tDQSQ
0.47
0.47
-
Average Clock LOW pulse width
DQS, DQS# to DQ skew, per group, per access
DQ output hold time from DQS, DQS#
DQ low-impedance time from CK, CK#
DQ high impedance time from CK, CK#
tQH
0.38
-450
-
225
225
tLZ(DQ)
tHZ(DQ)
-
-
AC150
10
-
Data setup time to DQS, DQS#
referenced to Vih(ac) / Vil(ac) levels
tDS(base)
AC135
DC100
ps
ps
Data hold time from DQS, DQS#
referenced to Vih(dc) / Vil(dc) levels
-
tDH(base)
45
-
-
-
-
-
-
-
DQ and DM Input pulse width for each input
DQS,DQS# differential READ Preamble
DQS, DQS# differential READ Postamble
DQS, DQS# differential output high time
DQS, DQS# differential output low time
DQS, DQS# differential WRITE Preamble
DQS, DQS# differential WRITE Postamble
tDIPW
tRPRE
tRPST
tQSH
360
0.9
0.3
0.4
0.4
0.9
0.3
ps
tCK
tCK
tCK
tCK
tCK
tCK
tQSL
tWPRE
tWPST
DQS, DQS# rising edge output access
time from rising CK, CK#
DQS and DQS# low-impedance time
(Referenced from RL - 1)
DQS and DQS# high-impedance time
(Referenced from RL + BL/2)
225
225
225
tDQSCK
tLZ(DQS)
tHZ(DQS)
-225
-450
-
ps
ps
ps
0.55
0.55
0.27
DQS, DQS# differential input low pulse width
DQS, DQS# differential input high pulse width
DQS, DQS# rising edge to CK, CK# rising edge
tDQSL
tDQSH
tDQSS
0.45
0.45
-0.27
tCK
tCK
tCK
DQS, DQS# falling edge setup time to
CK, CK# rising edge
-
tDSS
0.18
tCK
DQS, DQS# falling edge hold time from
CK, CK# rising edge
-
-
tDSH
0.18
512
tCK
tCK
DLL locking time
tDLLK
Confidential
-26／83-
Rev. 1.0 May 2016
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
