5800AND 5801
BiMOS II
LATCHED DRIVERS
5800 AND
5801
BiMOS II LATCHED DRIVERS
The UCN5800A/L and UCN5801A/EP/LW latched-input BiMOS
ICs merge high-current, high-voltage outputs with CMOS logic. The
CMOS input section consists of 4 or 8 data (‘D’ type) latches with
associated common CLEAR, STROBE, and OUTPUT ENABLE
circuitry. The power outputs are bipolar npn Darlingtons. This merged
technology provides versatile, flexible interface. These BiMOS power
interface ICs greatly benefit the simplification of computer or micropro-
cessor I/O. The UCN5800A and UCN5800L each contain four latched
drivers; the UCN5801A, UCN5801EP, and UCN5801LW contain eight
latched drivers.
UCN5800L
1
14
UCN5800A
OUTPUT
ENABLE
1
2
3
4
14
13
12
11
CLEAR
STROBE
V
SUPPLY
DD
OUT
1
IN
1
The UCN5800A/L and UCN5801A/EP/LW supersede the original
BiMOS latched-input driver ICs (UCN4400A and UCN4801A). These
second-generation devices are capable of much higher data input
rates and will typically operate at better than 5 MHz with a 5 V logic
supply. Circuit operation at 12 V affords substantial improvement over
the 5 MHz figure.
IN
2
OUT
2
5
6
10
9
OUT
3
IN
3
OUT
4
IN
4
7
8
COMMON
GROUND
The CMOS inputs are compatible with standard CMOS and NMOS
circuits. TTL circuits may mandate the addition of input pull-up resis-
tors. The bipolar Darlington outputs are suitable for directly driving
many peripheral/power loads: relays, lamps, solenoids, small dc
motors, etc.
Dwg. PP-014A
Note the UCN5800A (DIP) and the UCN5800L
(SOIC) are electrically identical and share a
common terminal number assignment.
All devices have open-collector outputs and integral diodes for
inductive load transient suppression. The output transistors are
capable of sinking 500 mA and will withstand at least 50 V in the OFF
state. Because of limitations on package power dissipation, the simul-
taneous operation of all drivers at maximum rated current can only be
accomplished by a reduction in duty cycle. Outputs may be paralleled
for higher load current capability.
ABSOLUTE MAXIMUM RATINGS
at +25°C Free-Air Temperature
Output Voltage, VCE . . . . . . . . . . . . . . 50 V
Supply Voltage, VDD . . . . . . . . . . . . . . 15 V
Input Voltage Range,
VIN . . . . . . . . . . . -0.3 V to VDD + 0.3 V
Continuous Collector Current,
lC . . . . . . . . . . . . . . . . . . . . . . 500 mA
Package Power Dissipation,
PD . . . . . . . . . . . . . . . . . . . . See Graph
Operating Temperature Range,
The UCN5800A is furnished in a standard 14-pin DIP; the
UCN5800L and UCN5801LW in surface-mountable SOICs; the
UCN5801A in a 22-pin DIP with 0.400" (10.16 mm) row centers; the
UCN5801EP in a 28-lead PLCC.
FEATURES
■ Output Transient Protection
■ To 4.4 MHz Data Input Rate ■ Internal Pull-Down Resistors
TA . . . . . . . . . . . . . . . . -20°C to +85°C
Storage Temperature Range,
■ High-Voltage,
■ Low-Power CMOS Latches
■ Automotive Capable
High-Current Outputs
■ CMOS, NMOS,
TTL Compatible Inputs
TS . . . . . . . . . . . . . . . -55°C to +150°C
Caution: CMOS devices have input static
protection but are susceptible to damage when
exposed to extremely high static electrical
charges.
Always order by complete part number, e.g., UCN5801EP .
ALLEGRO [ ALLEGRO MICROSYSTEMS ]
