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A3940KLP 参数 Datasheet PDF下载

A3940KLP图片预览
型号: A3940KLP
PDF下载: 下载PDF文件 查看货源
内容描述: 全桥式功率MOSFET控制器 [FULL-BRIDGE POWER MOSFET CONTROLLER]
分类和应用: 控制器
文件页数/大小: 12 页 / 633 K
品牌: ALLEGRO [ ALLEGRO MICROSYSTEMS ]
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3940  
FULL-BRIDGE POWER  
MOSFET CONTROLLER  
Functional Description  
Motor Lead Protection. A fault detection circuit monitors  
the voltage across the drain to source of the external MOSFETs.  
A fault is asserted “high” on the output terminal, FAULT, if the  
drain-to-source voltage of any MOSFET that is instructed to turn  
on is greater than the voltage applied to the VDSTH input terminal.  
When a high-side switch is turned on, the voltage from VDRAIN to  
the appropriate motor phase output, VSX, is examined. If the  
motor lead is shorted to ground the measured voltage will  
exceed the threshold and the FAULT terminal will go “high”.  
Similarly, when a low-side MOSFET is turned on, the differen-  
tial voltage between the motor phase (drain) and the LSS  
terminal (source) is monitored. VDSTH is set by a resistor divider  
Dead Time. The A3940 is intended to drive a wide range of  
power MOSFETs in applications requiring a wide range of  
switching times. In order to prevent cross conduction (a.k.a.  
shoot-through) during direction and PWM changes, a power  
MOSFET must be turned off before its “phase-pin mate” is  
turned on.  
tDEAD(ns) = K([18.8RDEAD(k)] + 50) + 90  
where K = 1 for LONG = 0; K = 32 for LONG = 1.  
Note: IDEAD(mA) 2/RDEAD(k), 12 k<RDEAD<500 kΩ.  
Sleep Mode. RESET = 0 clears any latched motor faults  
while driving all gate drive outputs low (coast). Eventually,  
RESET = 0 turns off all circuits to allow minimum current draw.  
to VREG5  
.
GHx and GLx outputs go high impedance (Z) when VREG13  
4 V. RESET = 1 enables the device after it powers up all  
<
To prevent erroneous motor faults during switching, the  
fault circuitry will wait two dead times after every PWM/phase  
change before monitoring the drain-to-source voltage; except, it  
will use one dead time for (1) a long coast to any phase on, or  
(2) a long hi-Z before on for that phase. This allows time for the  
motor output voltage to settle before checking for motor fault  
when using slow rise/fall gate-control waveforms.  
circuits. The user should wait the pump-up time, tup, to allow the  
device to be powered up properly before a gate output is  
enabled.  
Charge Pump. The A3940 is designed to accommodate a  
wide range of power supply voltages. The charge pump output  
voltage, VCP, is regulated to VBB + 11 V (or about 2VBB if  
VBB < 11 V).  
The VDRAIN is intended to be a Kelvin connection for the  
high-side, drain-source monitor circuit. Voltage drops across  
the power bus are eliminated by connecting an isolated PCB  
trace from the VDRAIN terminal to the drain of the MOSFET  
bridge. This allows improved accuracy in setting the VDSTH  
threshold voltage. The low-side, drain-source monitor uses the  
VREG13. A 13.3 V, low-dropout, linear regulator is used to  
power the low-side gate drive circuit directly and to provide the  
current to charge the bootstrap capacitors for the high-side gate  
drive. The input supply connection to this regulator, VIN, can  
be externally connected to the charge pump output, VCP, or it  
can be directly connected to the VBB or VBAT terminal.  
LSS terminal, rather than VDRAIN, in comparing against VDSTH  
.
Fault States. The FAULT terminal provides real time  
Internal current limiting protects VREG13  
.
indication of fault conditions after some digital noise filtering.  
The VDRAIN fault acts as if a short-to-ground fault existed on  
every motor phase. Bridge (or motor) faults are latched but  
cleared by a RESET = 0 pulse or by power cycling. GHx = GLx  
= 0 during RESET = 0. The undervoltage, overvoltage, and  
thermal shutdown faults are not latched and will not reset until  
the cause is eliminated. All faults cause, via the FAULT line, a  
coast and some cause shutdown of the regulators, as in the Fault  
Responses table (next page).  
VREG5. A 5 V, low-dropout, linear regulator is used to power  
the internal logic, regulators, and thermal detection. This  
regulator can also power low-current external resistor networks  
for VDSTH and OVSET, and the FAULT output pull-up. The  
input supply connection is VBB. Internal current limiting  
protects VREG5  
.
Power-Up State. If the input logic is open, internal pull-  
downs put the system in coast mode on powering up. First, issue  
a brake command for >10 µs to charge the bootstrap capacitors  
Note: As a test mode, if the thermal shutdown or SLEEP has not  
occurred and the FAULT output is externally held low, the coast  
mode and regulator shutdowns will not occur if motor or voltage  
faults occur. Do not wire-OR this terminal to other FAULT  
lines.  
and avoid a possible short-to-ground fault indication.  
www.allegromicro.com  
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