欢迎访问ic37.com |
会员登录 免费注册
发布采购

A3940KLP 参数 Datasheet PDF下载

A3940KLP图片预览
型号: A3940KLP
PDF下载: 下载PDF文件 查看货源
内容描述: 全桥式功率MOSFET控制器 [FULL-BRIDGE POWER MOSFET CONTROLLER]
分类和应用: 控制器
文件页数/大小: 12 页 / 633 K
品牌: ALLEGRO [ ALLEGRO MICROSYSTEMS ]
 浏览型号A3940KLP的Datasheet PDF文件第4页浏览型号A3940KLP的Datasheet PDF文件第5页浏览型号A3940KLP的Datasheet PDF文件第6页浏览型号A3940KLP的Datasheet PDF文件第7页浏览型号A3940KLP的Datasheet PDF文件第9页浏览型号A3940KLP的Datasheet PDF文件第10页浏览型号A3940KLP的Datasheet PDF文件第11页浏览型号A3940KLP的Datasheet PDF文件第12页  
3940  
FULL-BRIDGE POWER  
MOSFET CONTROLLER  
Terminal Descriptions  
CA/CB. High-side connection for bootstrap capacitor, positive  
supply for high-side gate drive. The bootstrap capacitor is  
charged to VREG13 – 1.5 V when the output Sx terminal is low.  
When the output swings high, the voltage on this terminal rises  
with the output to provide the boosted gate voltage needed for n-  
channel power MOSFETs.  
GLA/GLB. Low-side gate drive outputs for external, n-channel  
MOSFET drivers. External series gate resistors can control slew  
rate seen at the power driver gate.  
GND. Common ground and dc supply returns. Exposed  
thermal pad of LP package is NOT internally connected to  
GND.  
RESET. Control input to put device into minimum power  
consumption mode and to clear latched faults. Logic “1”  
enables the device; logic “0” triggers the sleep mode. Internally  
pulled down via 50 kresistor.  
LSS. Low-side gate drivers’ return. Connects to the common  
sources in the low-side of the power MOSFET bridge. It is the  
reference connection for the short-to-battery monitor.  
OVSET. A positive, dc level that controls the VBB overvoltage  
trip point. Usually, provided from precision resistor divider  
network between VREG5 and GND. If connected directly to  
VREG5, sets unspecified but high overvoltage trip point, effec-  
tively eliminating the overvoltage protection.  
ENABLE. Logic “1” enables direct control of the output  
drivers via the PHASE input, as in PWM controls, and ignores  
the MODE and SR inputs. Internally pulled down via 50 kΩ  
resistor.  
MODE. Logic input to set the current decay mode. Logic “1”  
(slow-decay mode) switches off the high-side MOSFET in  
response to a PWM “off” command. Logic “0” (fast-decay  
mode) switches off both the high-side and low-side MOSFETs.  
Internally pulled down via 50 kresistor.  
SA/SB. Directly connected to the motor terminals, these  
terminals sense the voltages switched across the load and are  
connected to the negative side of the bootstrap capacitors. Also,  
are the negative supply connection for the floating, high-side  
drivers.  
PHASE. Motor direction control. When logic “1”, enables  
gate drive outputs GHA and GLB allowing current flow from  
SA to SB. When logic “0”, enables GHB and GLA allowing  
current flow from SB to SA. Internally pulled down via 50 kΩ  
resistor.  
VBB. Positive supply voltage. Usually connected to the motor  
voltage supply. If VBB is above a specified level or below a  
specified level, a fault will be asserted.  
VDRAIN. Kelvin connection for drain-to-source voltage (short-  
to-ground) monitor and is connected to high-side drains of the  
MOSFET bridge. Also used to detect “open drain”.  
SR. When logic “1”, enables synchronous rectification; logic  
“0” disables the synchronous rectification. Internally pulled  
down via 50 kresistor.  
VDSTH. A positive, dc level that sets the short-to-ground and  
short-to-battery monitor threshold voltage. If the drain-source  
voltage exceeds this level (after the dead time) during an “on”  
state, a fault will be asserted.  
FAULT. Open drain, diagnostic logic output signal. When  
logic “1”, indicates that one or more fault conditions have  
occurred. Use an external pullup resistor to VREG5 or to digital  
controller. Internally causes a coast when asserted. See also  
Functional Description, next page.  
CP1 [CP2]. Charge pump capacitor negative [positive] side. If  
not using the charge pump, leave both terminals open.  
IDEAD. Analog current set by resistor (12 k<RDEAD<500 k)  
to ground. In conjunction with LONG, determines dead time  
between GHx and GLx transitions of same phase. VIDEAD = 2 V.  
VCP. Charge pump output for VREG13 input. If not using the  
charge pump, connect this terminal to VBB.  
VIN. Positive supply voltage for the VREG13 linear regulator.  
Usually connected to VCP, the charge-pump output gate drive.  
If not using the charge pump, connect VIN to VBB or other dc  
supply greater than 11 V.  
LONG. When logic “1”, selects long dead time between GHx  
and GLx transitions of same phase. When logic “0”, selects  
short dead times. Internally pulled down via 50 kresistor.  
GHA/GHB. High-side gate-drive outputs for n-channel  
MOSFET drivers. External series gate resistors can control slew  
rate seen at the power driver gate.  
VREG13. High-side, gate-driver supply. If VREG13 falls below  
a specified level, a fault will be asserted.  
VREG5. Regulated 5 V output for internal logic.  
115 Northeast Cutoff, Box 15036  
Worcester, Massachusetts 01615-0036 (508) 853-5000  
8