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A3940KLP 参数 Datasheet PDF下载

A3940KLP图片预览
型号: A3940KLP
PDF下载: 下载PDF文件 查看货源
内容描述: 全桥式功率MOSFET控制器 [FULL-BRIDGE POWER MOSFET CONTROLLER]
分类和应用: 控制器
文件页数/大小: 12 页 / 633 K
品牌: ALLEGRO [ ALLEGRO MICROSYSTEMS ]
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3940  
FULL-BRIDGE POWER  
MOSFET CONTROLLER  
ELECTRICAL CHARACTERISTICS: unless otherwise noted at TA = -40°C to +135°C, TJ = -40°C to +150°C,  
VIN VBB = 7 V to 40 V, Cp = 0.47 µF, Cr = 1 µF, CREG5 = 0.1 µF, CREG13 = 10 µF, CBOOT = 0.1 µF, PWM = 22.5 kHz  
square wave.  
Limits  
Characteristics  
Control Logic  
Symbol  
Conditions  
Min  
Typ  
Max  
Units  
Logic Input Voltage  
VIN(1)  
VIN(1)  
VIN(0)  
IIN(1)  
HIGH level input (Logic 1), except RESET.  
HIGH level input (Logic 1) for RESET  
LOW level input (Logic 0)  
VIN = 2.0 V  
2.0  
2.2  
V
V
0.8  
100  
40  
1.0  
V
Logic Input Current  
40  
16  
µA  
µA  
µA  
IIN(0)  
VIN = 0.8 V, except RESET(0)  
VIN = 0.8 V, RESET(0)  
IIN(0)  
Gate Drives, GHx, GLx ( internal SOURCE or upper switch stages)  
Output High Voltage  
VDSL(H)  
IxU  
rSDU(on)  
tr  
GHx: IxU = -10 mA, Vsx = 0  
GLx: IxU = -10 mA, Vlss = 0  
VSDU = 10 V, TJ = 25°C  
VREG13 - 2.2  
VREG13  
VREG13  
V
V
VREG13 - 0.2  
Source Current (pulsed)  
Source ON Resistance  
Source Load Rise Time  
700  
mA  
mA  
VSDU = 10 V, TJ = 135°C  
400  
4.0  
7.0  
IxU = -150 mA, TJ = 25°C  
13  
IxU = -150 mA, TJ = 135°C  
Measure VDSL, 20% to 80%, CL = 3300 pF  
23  
90  
ns  
Gate Drives, GHx, GLx ( internal SINK or lower switch stages)  
Output Low Voltage  
Sink Current (pulsed)  
Sink ON Resistance  
Sink Load Fall Time  
VDSL(L)  
IxL  
rDSL(on)  
tf  
GHx: IxL = 10 mA, Vsx = 0  
GLx: IxL = 10 mA, Vlss = 0  
VDSL = 10 V, TJ = 25°C  
150  
150  
mV  
mV  
mA  
mA  
800  
VDSL = 10 V, TJ = 135°C  
550  
1.8  
3.0  
IxL = +150 mA, TJ = 25°C  
IxL = +150 mA, TJ = 135°C  
Measure VDSL, 80% to 20%, CL = 3300 pF  
6.0  
7.5  
70  
ns  
Gate Drives, GHx, GLx (General)  
Propagation Delay  
tpd  
Logic input to unloaded GHx, GLx  
225  
50  
ns  
ns  
µs  
µs  
µs  
µs  
Output Skew Time  
tsk(o)  
tdead  
Grouped by rising or falling edge  
Dead Time  
LONG = 0, RDEAD = 12.1 k(IDEAD = 167 µA)  
LONG = 0, RDEAD = 499 k(IDEAD = 4 µA)  
LONG = 1, RDEAD = 12.1 k(IDEAD = 167 µA)  
LONG = 1, RDEAD = 499 k(IDEAD = 4 µA)  
0.3  
(Shoot-Through Prevention)  
Between GHx, GLx transitions  
of same phase  
11.0  
8.3  
345  
NOTES: Typical Data is for design information only.  
Negative current is defined as coming out of (sourcing) the specified device terminal.  
For GHX: VSDU = VCX – VGHX, VDSL = VGHX – VSX, VDSL(H) = VCX – VSDU – VSX  
.
For GLX: VSDU = VREG – VGLX, VDSL = VGLX – VLSS, VDSL(H) = VREG – VSDU – VLSS.  
Continued next page …  
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