[AK8975/C]
7.2. I2C Bus Interface
The I2C bus interface of AK8975/C supports the standard mode (100 kHz max.) and the fast mode (400 kHz
max.).
7.2.1. Data Transfer
To access AK8975/C on the bus, generate a start condition first.
Next, transmit a one-byte slave address including a device address. At this time, AK8975/C compares the slave
address with its own address. If these addresses match, AK8975/C generates an acknowledgement, and then
executes READ or WRITE instruction. At the end of instruction execution, generate a stop condition.
7.2.1.1. Change of Data
A change of data on the SDA line must be made during "Low" period of the clock on the SCL line. When the
clock signal on the SCL line is "High", the state of the SDA line must be stable. (Data on the SDA line can be
changed only when the clock signal on the SCL line is "Low".)
During the SCL line is "High", the state of data on the SDA line is changed only when a start condition or a
stop condition is generated.
SCL
SDA
DATA LINE
STABLE :
DATA VALID
CHANGE
OF DATA
ALLOWED
Figure 7.3 Data Change
7.2.1.2. Start/Stop Condition
If the SDA line is driven to "Low" from "High" when the SCL line is "High", a start condition is generated.
Any instruction starts with a start condition.
If the SDA line is driven to "High" from "Low" when the SCL line is "High", a stop condition is generated.
Any instruction stops with a stop condition.
SCL
SDA
START CONDITION
STOP CONDITION
Figure 7.4 Start and Stop Conditions
MS1187-E-02
- 18 -
2010/05
AKM [ ASAHI KASEI MICROSYSTEMS ]
