[AK8975/C]
5.3.5. I2C Bus Interface
CSB pin = “H”
I2C bus interface is compliant with Standard mode and Fast mode. Standard/Fast mode is selected
automatically by fSCL.
(1) Standard mode
fSCL≤100kHz
1.65V≤Vid≤Vdd
Symbol
fSCL
tHIGH
tLOW
Parameter
SCL clock frequency
SCL clock "High" time
Min.
Typ.
Max.
100
Unit
kHz
μs
4.0
4.7
SCL clock "Low" time
μs
tR
tF
SDA and SCL rise time
SDA and SCL fall time
1.0
0.3
μs
μs
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tSU:STO
tBUF
Start Condition hold time
Start Condition setup time
SDA hold time (vs. SCL falling edge)
SDA setup time (vs. SCL rising edge)
Stop Condition setup time
Bus free time
4.0
4.7
0
250
4.0
4.7
μs
μs
μs
ns
μs
μs
(2) Fast mode
100kHz<fSCL≤400kHz
1.65V≤Vid≤Vdd
Symbol
Parameter
SCL clock frequency
Min.
Typ.
Max.
400
Unit
kHz
μs
μs
μs
fSCL
tHIGH
tLOW
tR
SCL clock "High" time
SCL clock "Low" time
SDA and SCL rise time
0.6
1.3
0.3
0.3
tF
SDA and SCL fall time
μs
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tSU:STO
tBUF
Start Condition hold time
Start Condition setup time
SDA hold time (vs. SCL falling edge)
SDA setup time (vs. SCL rising edge)
Stop Condition setup time
Bus free time
0.6
0.6
0
100
0.6
1.3
μs
μs
μs
ns
μs
μs
tSP
Noise suppression pulse width
50
ns
[I2C bus interface timing]
1/fSCL
VIH3
VIL3
SCL
VIH3
SDA
VIL3
tLOW tR
tHIGH
tBUF
tF
tSP
VIH3
VIL3
SCL
tHD:STA
Stop Start
tHD:DAT
tSU:DAT tSU:STA
Start
tSU:STO
Stop
MS1187-E-02
- 10 -
2010/05
AKM [ ASAHI KASEI MICROSYSTEMS ]
