ASAHI KASEI
[AK5392]
SWITCHING CHARACTERISTICS
(Ta=25°C; VA=5.0V±5%;VD=3.0 5.25V; CL=20pF)
Parameter
Control Clock Frequency
Master Clock 256fs:
Pulse width Low
Symbol
Min
Typ
Max
Units
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fSLK
fs
0.256
29
12.288
13.824
MHz
ns
Pulse width High
29
ns
384fs:
0.384
20
18.432
20.736
MHz
ns
Pulse width Low
Pulse width High
20
ns
Serial Data Output Clock (SCLK)
Channel Select Clock (LRCK)
duty cycle
6.144
48
6.912
54
MHz
kHz
%
1
25
75
Serial Interface Timing
Slave Mode(SMODE1="L")
SCLK Period
(Note 9 )
tSLK
tSLKL
tSLKH
tSLR
tDLR
tDSS
tSF
144.7
65
ns
ns
ns
ns
ns
ns
ns
SCLK Pulse Width Low
Pulse width High
65
SCLK falling to LRCK Edge (Note 10 )
LRCK Edge to SDATA MSB Valid
SCLK falling to SDATA Valid
SCLK falling to FSYNC Edge
Master Mode(SMODE1="H")
SCLK Frequency
-45
45
45
45
45
-45
-20
fSLK
128fs
50
Hz
%
duty cycle
FSYNC Frequency
fFSYNC
2fs
Hz
%
duty cycle
50
SCLK falling to LRCK Edge
LRCK Edge to FSYNC rising
SCLK falling to SDATA Valid
SCLK falling to FSYNC Edge
Reset/Calibration timing
RST Pulse width
RST falling to CAL rising
RST rising to CAL falling
RST rising to SDATA Valid (Note 11 )
Notes: 9 . Refer to Serial Data interface.
tSLR
tLRF
tDSS
tSF
20
ns
tslk
ns
ns
1
45
20
-20
tRTW
tRCR
tRCF
tRTV
150
ns
ns
50
(Note 11 )
8704
8960
1/fs
1/fs
10 . Specified LRCK edges not to coincide with the rising edges of SCLK.
11 .The number of the LRCK rising edges after RST brought high. The value is in master mode.
In slave mode it becomes one LRCK clock(1/fs) longer.
0188-E-01
1997/11
- 8 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
