ASAHI KASEI
[AK5392]
OPERATION OVERVIEW
System Clock Input
The external clocks which are required to operate the AK5392 are MCLK, LRCK(fs),SCLK. MCLK should be
synchronized with LRCK but the phase is free of care. MCLK can be either 256fs or 384fs by setting CMODE pin.
When the 384fs is selected, the internal master clock becomes 256fs(=384fs*2/3). Table 1 illustrates standard
audio word rates and corresponding frequencies used in the AK5392.
As the AK5392 includes the phase detect circuit for LRCK, the AK5392 is reset automatically when the
synchronization is out of phase by changing the clock frequencies.Therefore, the reset is only needed for power-up.
MCLK
fs
SCLK(128fs)
256fs
384fs
32.0kHz
44.1kHz
48.0kHz
8.1920MHz 12.2880MHz
11.2896MHz 16.9344MHz
12.2880MHz 18.4320MHz
4.0960MHz
5.6448MHz
6.1440MHz
Table 1 . Examples of System Clock
Serial Data Interface
AK5392 supports four serial data formats which can be selected via SMODE1 and SMODE2 pins(Table 2 ).The
data format is MSB-first, 2's complement.
Figure
Figure 1
Figure 2
Figure 3
Figure 4
SMODE2 SMODE1
Mode
Slave Mode
LRCK
L
L
L
H
L
Lch=H, Rch=L
Lch=H, Rch=L
Lch=L, Rch=H
Lch=L, Rch=H
Master Mode
I2S Slave Mode
I2S Master Mode
H
H
H
Table 2 . Serial I/F Format
0188-E-01
1997/11
- 11 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
