ASAHI KASEI
[AK5392]
14
SCLK
I/O Serial Data Clock Pin
Data is clocked out on the falling edge of SCLK.
Slave mode:
SCLK requires more than 48fs clock.
Master mode:
SCLK outputs a 128fs clock. SCLK stays "L" during reset.
Serial Data Output Pin
15
16
SDATA
O
MSB first, 2's complement. SDATA stays "L" during reset.
FSYNC
I/O Frame Synchronization Signal Pin
Slave mode:
When "H", the data bits are clocked out on SDATA.
Master mode:
FSYNC outputs 2fs clock.
FSYNC stays "L" during reset.
17
18
19
20
CLK
I
I
I
I
Master Clock Input Pin
CMODE="H":384fs
CMODE="L":256fs
CMODE
HPFE
TEST
Master Clock Select Pin
"L": CLK=256fs (12.288MHz @fs=48kHz)
"H": CLK=384fs (18.432MHz @fs=48kHz)
High Pass Filter Enable Pin
"L": Disable
"H": Enable
Test Pin
Should be connected DGND.
Substrate Ground Pin, 0V
Analog Ground Pin, 0V
21
22
23
24
25
26
27
28
BGND
AGND
VA
-
-
-
Analog Supply Pin, 5V
AINR-
AINR+
VCOMR
GNDR
VREFR
I
Rch Analog negative input Pin
Rch Analog positive input Pin
Rch Common Voltage Pin, 2.5V
Rch Reference Ground Pin, 0V
Rch Reference Voltage Pin, 3.75V
Normally connected to GNDR with a 10uF electrolytic capacitor and
a 0.1uF ceramic capacitor
I
O
-
O
0188-E-01
1997/11
- 4 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
