[AK5358B]
SWITCHING CHARACTERISTICS
(Ta=-20°C
∼
85°C; VA=4.5
∼
5.5V; VD=2.7
∼
5.5V; C
L
=20pF)
Parameter
Symbol
min
Master Clock Timing
2.048
fCLK
512fs, 256fs Frequency
40
dCLK
Duty cycle
3.072
fCLK
768fs, 384fs Frequency
40
dCLK
Duty cycle
LRCK Frequency
fs
8
Duty Cycle
Slave mode
45
Master mode
Audio Interface Timing
Slave mode
160
tSCK
SCLK Period
65
tSCKL
SCLK Pulse Width Low
65
tSCKH
Pulse Width High
30
tLRSH
LRCK Edge to SCLK “↑”
30
tSHLR
SCLK “↑” to LRCK Edge
tLRS
LRCK to SDTO (MSB) (Except I
2
S mode)
tSSD
SCLK “↓” to SDTO
Master mode
fSCK
SCLK Frequency
dSCK
SCLK Duty
−20
tMSLR
SCLK “↓” to LRCK
−20
tSSD
SCLK “↓” to SDTO
typ
max
24.576
60
36.864
60
96
55
Units
MHz
%
MHz
%
kHz
%
%
50
35
35
64fs
50
20
35
ns
ns
ns
ns
ns
ns
ns
Hz
%
ns
ns
ns
1/fs
1/fs
Reset Timing
tPD
150
PDN Pulse Width
tPDV
4132
PDN “↑” to SDTO valid at Slave Mode (Note
tPDV
4129
PDN “↑” to SDTO valid at Master Mode (Note
Note 11. The AK5358B is reset by more than 13us “L” period of MCLK. The data is output after initializing.
Note 12. SCLK rising edge must not occur at the same time as LRCK edge.
Note 13. The AK5358B can be reset by bringing the PDN pin = “L”.
Note 14. This cycle is the number of LRCK rising edges from the PDN pin = “H”.
MS1155-E-00
-8-
2010/02
AKM [ ASAHI KASEI MICROSYSTEMS ]
