[AK5358B]
■ Audio Interface Format
Two kinds of data formats can be selected by the DIF pin (Table 3). In both modes, the serial data is in MSB first, 2’s
compliment format. The SDTO is clocked out on the falling edge of SCLK. The audio interface supports both master and
slave modes. In master mode, SCLK and LRCK are output with the SCLK frequency fixed to 64fs and the LRCK
frequency fixed to 1fs.
Mode
0
1
DIF pin
SDTO
24bit, MSB justified
24bit, I2S Compatible
LRCK
H/L
L/H
SCLK
Figure
Figure 1
Figure 2
L
H
≥ 48fs or 32fs
≥ 48fs or 32fs
Table 3. Audio Interface Format
LRCK
0 1
2
20 21 22 23 24
31 0 1 2
23 22
20 21 22 23 24
31 0 1
SCLK(64fs)
SDTO(o)
23 22
4 3 2 1 0
4 3 2 1 0
Rch Data
23
23:MSB, 0:LSB
Lch Data
Figure 1. Mode 0 Timing
LRCK
0 1 2 3
21 22 23 24 25
0 1 2
21 22 23 24 25
0 1
SCLK(64fs)
SDTO(o)
23 22
4 3 2 1 0
23 22
4 3 2 1 0
Rch Data
23:MSB, 0:LSB
Lch Data
Figure 2. Mode 1 Timing
■ Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.0Hz
(@fs=48kHz) and it scales with sampling rate (fs).
MS1155-E-00
2010/02
- 12 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
