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AK5353VT 参数 Datasheet PDF下载

AK5353VT图片预览
型号: AK5353VT
PDF下载: 下载PDF文件 查看货源
内容描述: 与SIGLE端输入96kHz的24位ADC [96kHz 24BIT ADC WITH SIGLE-ENDED INPUT]
分类和应用: 转换器模数转换器光电二极管输入元件
文件页数/大小: 17 页 / 116 K
品牌: AKM [ ASAHI KASEI MICROSYSTEMS ]
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ASAHI KASEI  
[AK5353]  
OPERATION OVERVIEW  
n
System Clock Input  
The external clocks which are required to operate the AK5353 are MCLK(256fs/384fs/512fs), LRCK(1fs), SCLK.  
MCLK should be synchronized with LRCK but the phase is not critical. When 384fs or 512fs clock is input to MCLK pin,  
the internal master clock becomes 256fs(=384fs*2/3=512fs*1/2). Table 1 illustrates standard audio word rates and  
corresponding frequencies used in the AK5353.  
All external clocks (MCLK,BICK,LRCK) should always be present whenever the AK5353 is in normal operation mode  
(PDN= H ). If these clocks are not provided, the AK5353 may draw excess current and may not possibly operate properly  
because the device utilizes dynamic refreshed logic internally. If the external clocks are not present, the AK5353 should  
be in the power-down mode (PDN= L ). After exiting reset at power-up etc., the AK5353 is in the power-down mode  
until MCLK and LRCK are input.  
fs  
MCLK  
384fs  
SCLK  
64fs  
256fs  
512fs  
32fs  
128fs  
32.0kHz  
8.1920MHz 12.2880MHz 16.3840MHz  
1.0240MHz  
1.4112MHz  
1.5360MHz  
3.0720MHz  
2.0480MHz  
2.8224MHz  
3.0720MHz  
6.1440MHz  
4.0960MHz  
5.6448MHz  
6.1440MHz  
N/A  
44.1kHz 11.2896MHz 16.9344MHz 22.5792MHz  
48.0kHz 12.2880MHz 18.4320MHz 24.5760MHz  
96.0kHz 24.5760MHz 36.8640MHz  
N/A  
Table 1. Example of System Clock  
n
Serial Data Interface  
2 kinds of data format can be selected by DIF pin. The data is clocked out via the SDTO pin by SCLK corresponding to  
the setting of DIF pin. The format of output data is 2 s complement MSB first.  
Mode  
0
1
DIF  
0
1
Format  
24bit, MSB justified, L/R, SCLK 48fs (16bit, MSB justified, L/R, SCLK 32fs)  
24bit, I2S,  
SCLK 48fs (16bit, I2S,  
SCLK 32fs)  
Table 2. Audio Serial Interface Formats  
M0067-E-00  
1999/06  
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