ASAHI KASEI
[AK5353]
SWITCHING CHARACTERISTICS (VA,VD=4.5∼5.5V)
(Ta=25°C; VA,VD=4.5∼5.5V; C
L
=20pF)
Parameter
Symbol
min
typ
Control Clock Frequency
Master Clock 256fs:
fCLK
1.024
12.288
Pulse Width Low
tCLKL
16
Pulse Width High
tCLKH
16
384fs:
fCLK
1.536
18.432
Pulse Width Low
fCLKL
10
Pulse Width High
fCLKH
10
512fs:
fCLK
2.048
24.576
Pulse Width Low
fCLKL
16
Pulse Width High
fCLKH
16
SCLK Frequency
fSLK
LRCK Frequency
fs
48
4
Serial Interface Timing
(Note 12)
tSLK
160
SCLK Period
tSLKL
65
SCLK Pulse Width Low
tSLKH
65
Pulse Width High
tLRSH
30
LRCK Edge to SCLK
↑
(Note 13)
tSHLR
30
SCLK
↑
to LRCK Edge
(Note 13)
tDLR
LRCK Edge to SDTO Valid
(Note 14)
tDSS
SCLK
↓
to SDTO Valid
Power-Down & Reset Timing
PDN Pulse Width
tPDW
150
tPDV
4129
PDN
↓
to SDTO delay
(Note 15)
Note:12. Refer to the operating overview section Serial Data Interface .
13. SCLK rising edge must not occur at the same time as LRCK edge.
14. In case of MSB justified format.
15. These cycles are the number of LRCK rising from PDN falling.
max
24.576
Units
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
MHz
kHz
ns
ns
ns
ns
ns
ns
ns
ns
1/fs
36.864
24.576
6.144
96
50
50
M0067-E-00
-8-
1999/06
AKM [ ASAHI KASEI MICROSYSTEMS ]
