[AK4958]
Parameter
Symbol
min
typ
max
Unit
PLL Slave Mode (PLL Reference Clock = BICK pin)
LRCK Input Timing
PLL3-0 bits = “0010”
PLL3-0 bits = “0011”
fs
fs
Duty
-
-
45
fBCK/32
fBCK/64
-
-
-
55
Hz
Hz
%
Frequency
Duty
BICK Input Timing
Frequency
PLL3-0 bits = “0010”
PLL3-0 bits = “0011”
fBCK
fBCK
tBCKL
tBCKH
0.2352
0.4704
0.4/fBCK
0.4/fBCK
-
-
-
-
1.536
3.072
-
-
MHz
MHz
s
s
Pulse Width Low
Pulse Width High
External Slave Mode
MCKI Input Timing
Frequency
FS1-0 bits = “00”
FS1-0 bits = “01”
FS1-0 bits = “10” or “11”
fCLK
fCLK
fCLK
tCLKL
tCLKH
-
-
-
256fs
1024fs
512fs
-
-
-
-
-
-
-
Hz
Hz
Hz
s
Pulse Width Low
Pulse Width High
0.4/fCLK
0.4/fCLK
s
LRCK Input Timing
Frequency
FS1-0 bits = “00”
fs
fs
fs
fs
Duty
7.35
7.35
7.35
7.35
45
-
-
-
-
-
48
13
24
48
55
kHz
kHz
kHz
kHz
%
FS1-0 bits = “01”
FS1-0 bits = “10”
FS1-0 bits = “11”
Duty
BICK Input Timing
Frequency
fBCK
tBCKL
tBCKH
32fs
130
130
-
-
-
64fs
-
-
Hz
ns
ns
Pulse Width Low
Pulse Width High
External Master Mode
MCKI Input Timing
Frequency
256fs (FS1-0 bits = “00”)
fCLK
fCLK
fCLK
fCLK
tCLKL
tCLKH
1.8816
3.7632
3.7632
7.5264
0.4/fCLK
0.4/fCLK
-
-
-
-
-
-
12.288
13.312
24.576
13.312
-
MHz
MHz
MHz
MHz
s
512fs (FS1-0 bits = “10”)
512fs (FS1-0 bits = “11”)
1024fs (FS1-0 bits = “01”)
Pulse Width Low
Pulse Width High
-
s
LRCK Output Timing
Frequency
FS1-0 bits = “00”
FS1-0 bits = “01”
FS1-0 bits = “10” or “11”
fs
fs
fs
-
-
-
-
fCLK/256
fCLK/1024
fCLK/512
50
-
-
-
-
kHz
kHz
kHz
%
Duty Cycle
Duty
BICK Output Timing
Frequency
BCKO bit = “0”
BCKO bit = “1”
fBCK
fBCK
dBCK
-
-
-
32fs
64fs
50
-
-
-
Hz
Hz
%
Duty Cycle
MS1558-J-01-PB
2013/10
- 22 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
