[AK4958]
スイッチング特性
(Ta =25C; fs=48kHz; CL=20pF; AK4958ECB: AVDD=2.8 3.6V, DVDD = 1.6 ~ 2.0V, TVDD = 1.6 or (DVDD-0.2)
3.6V, AK4958ECB: AVDD=2.8 3.6V, DTVDD = 1.6 ~ 2.0V)
Parameter
Symbol
min
typ
max
Unit
PLL Master Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
PLL3-0 bits = “0100”
PLL3-0 bits = “0110”
PLL3-0 bits = “0111”
PLL3-0 bits = “1100”
PLL3-0 bits = “1101”
fCLK
fCLK
fCLK
fCLK
fCLK
tCLKL
tCLKH
-
-
-
-
11.2896
-
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
s
12
24
13.5
27
-
-
Pulse Width Low
Pulse Width High
0.4/fCLK
0.4/fCLK
-
s
MCKO Output Timing
Frequency
PS1-0 bits = “00”
PS1-0 bits = “01”
PS1-0 bits = “10”
PS1-0 bits = “11” (Note 33)
fMCK
fMCK
fMCK
fMCK
dMCK
-
-
-
-
40
256fs
128fs
64fs
512fs
50
-
-
-
-
60
Hz
Hz
Hz
Hz
%
Duty Cycle
LRCK Output Timing
Frequency
fs
Duty
-
-
Table 6
50
-
-
Hz
%
Duty Cycle
BICK Output Timing
Frequency
BCKO bit = “0”
BCKO bit = “1”
fBCK
fBCK
dBCK
-
-
-
32fs
64fs
50
-
-
-
Hz
Hz
%
Duty Cycle
PLL Slave Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
tCLKL
tCLKH
11.2896
0.4/fCLK
0.4/fCLK
-
-
-
27
-
-
MHz
s
s
Pulse Width Low
Pulse Width High
MCKO Output Timing
Frequency
PS1-0 bits = “00”
PS1-0 bits = “01”
PS1-0 bits = “10”
PS1-0 bits = “11” (Note 33)
fMCK
fMCK
fMCK
fMCK
dMCK
-
-
-
-
40
256fs
128fs
64fs
512fs
50
-
-
-
-
60
Hz
Hz
Hz
Hz
%
Duty Cycle
LRCK Input Timing
Frequency
fs
Duty
-
45
Table 6
-
-
55
Hz
%
Duty
BICK Input Timing
Frequency
fBCK
tBCKL
tBCKH
32fs
0.4 x tBCK
0.4 x tBCK
-
-
-
64fs
-
-
Hz
s
s
Pulse Width Low
Pulse Width High
Note 33. MCKO=512fs時はfs=8, 11.025, 12, 16, 32kHzは使用できません。
MS1558-J-01-PB
2013/10
- 21 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
