[AK4753]
LRCK
(Master)
LRCK
(Slave)
14
63
63
63
0
1
2
15 16 17 22 23 24 25 26 30 31 32 33 34 35 36 37 59 60 61 62 63
0
BICK(64fs)
SDTI(i)
Lch
Rch
15
15 14 13
1
0
9
8
7
6
1
0
1/fs
15:MSB, 0:LSB
Figure 27. Mode 0 Timing (BCKP bit= “0”, MSBS bit= “0”)
LRCK
(Master)
LRCK
(Slave)
14
0
1
2
15 16 17 22 23 24 25 26 30 31 32 33 34 35 36 37 59 60 61 62 63
0
BICK(64fs)
SDTI(i)
Lch
Rch
15 14 13
1
0
15
9
8
7
6
1
0
1/fs
15:MSB, 0:LSB
Figure 28. Mode 0 Timing (BCKP bit= “1”, MSBS bit= “0”)
LRCK
(Master)
LRCK
(Slave)
14
0
1
2
15 16 17 22 23 24 25 26 30 31 32 33 34 35 36 37 59 60 61 62 63
0
BICK(64fs)
SDTI(i)
Lch
Rch
15 14 13
1
0
15
9
8
7
6
1
0
1/fs
15:MSB, 0:LSB
Figure 29. Mode 0 Timing (BCKP bit= “0”, MSBS bit= “1”)
LRCK
(Master)
LRCK
(Slave)
14
63
0
1
2
15 16 17 22 23 24 25 26 30 31 32 33 34 35 36 37 59 60 61 62 63
0
BICK(64fs)
SDTI(i)
Lch
Rch
15 14 13
1
0
15
9
8
7
6
1
0
1/fs
15:MSB, 0:LSB
Figure 30. Mode 0 Timing (BCKP bit= “1”, MSBS bit= “1”)
MS1311-E-00
2011/07
- 28 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
