CONFIDENTIAL
[AK4753]
■ Timing Diagram
1/fCLK
tACW tACW
1000pF
Measurement
Point
MCKI Input
VAC
100kΩ
VSS2
VSS2
Figure 3. MCKI AC Coupling Timing
1/fCLK
VIH
VIL
MCKI
LRCK
BICK
tCLKH
tCLKL
1/fs
50%DVDD
tLRCKH
tLRCKL
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
tBCK
50%DVDD
tBCKH
tBCKL
dBCK = tBCKH / tBCK x 100
tBCKL / tBCK x 100
Figure 4. Clock Timing (PLL/EXT Master mode)
tLRCKH
LRCK
50%DVDD
tDBF
BICK
(BCKP = "0")
50%DVDD
50%DVDD
BICK
(BCKP = "1")
tSDS
tSDH
VIH
VIL
SDTI
Figure 5. Audio Interface Timing (PLL/EXT Master mode, DSP mode, MSBS = “0”)
MS1311-E-00
2011/07
- 14 -