CONFIDENTIAL
Symbol
[AK4753]
Parameter
min
typ
max
Units
Control Interface Timing (I2C bus-slave): SCL, SDA pins (Note 19)
SCL Clock Frequency
fSCL1
tBUF1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
400
-
-
-
-
-
-
-
0.3
0.3
400
-
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
pF
μs
ns
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
1.3
0.6
1.3
0.6
0.6
0
0.1
-
-
tHD1:STA
tLOW1
tHIGH1
tSU1:STA
tHD1:DAT
tSU1:DAT
tR1
tF1
Cb1
tSU1:STO
tSP1
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 20)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Capacitive Load on Bus
-
0.6
0
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
50
EEP-ROM Control Interface Timing (I2C bus-master): EESCL, EESDA pins (Note 19)
EESCL Clock Frequency
fSCL2
tBUF2
200
1.3
0.6
1.3
0.6
0.6
0
0.1
-
-
280
400
-
-
-
-
-
0.9
-
0.3
0.3
400
-
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
pF
μs
ns
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
-
-
-
-
-
-
-
-
-
-
-
-
tHD:STA2
tLOW2
tHIGH2
tSU2:STA
tHD2:DAT
tSU2:DAT
tR2
tF2
Cb2
tSU2:STO
tSP2
Clock High Time
Setup Time for Repeated Start Condition
EESDA Hold Time from EESCL Falling (Note 20)
EESDA Setup Time from EESCL Rising
Rise Time of Both EESDA and EESCL Lines
Fall Time of Both EESDA and EESCL Lines
Capacitive Load on Bus
-
0.6
0
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
50
Power-down & Reset Timing
PDN Pulse Width (Note 21)
tPD
10
-
-
ms
Note 19. I2C-bus is a trademark of NXP B.V.
Note 20. Data must be held long enough to bridge the 300ns-transition time of SCL and EESCL.
Note 21. The AK4753 can be reset by the PDN pin = “L”.
MS1311-E-00
2011/07
- 13 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
