[AK4685]
■ DAC1/2 Clock Control
The master clock MCLKA (MCLKC) must be synchronized with LRCKA (LRCKC) but the phase is not critical. After
exiting reset state when power-up the device or other situations (PDN pin = “H”), the DAC is in power-down mode until
MCLKA/C and LRCKA/C are input.
There are two modes for controlling the sampling speed of DAC1(DAC2). One is the Manual Setting Mode (ACKS bit =
“0”) using the DFS1-0 bits, and the other is Auto Setting Mode (ACKS bit = “1”).
1. Manual Setting Mode (ACKS1(ACKS2) bit = “0”)
When the ACKS1(ACKS2) bit = “0”, DAC1(DAC2) is in Manual Setting Mode and the sampling speed is selected by
DFS11-10, DFS21-20 bits (Table 4).
DFS11
DFS10
DAC1(DAC2) Sampling Speed fs
(DFS21)
(DFS20)
(default)
0
0
1
1
0
1
0
1
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Not Available
32kHz~48kHz
64kHz~96kHz
120kHz~192kHz
-
(Note: ADC is always in Normal Speed Mode)
Table 4. DAC Sampling Speed (ACKS1/2 bit = “0”, Manual Setting Mode)
LRCKA/C MCLKA/C (MHz)
BICKA/C (MHz)
64fs
fs
256fs
8.1920
11.2896
12.2880
384fs
512fs
768fs
32.0kHz
44.1kHz
48.0kHz
12.2880
16.9344
18.4320
16.3840
22.5792
24.5760
24.5760
33.8688
36.8640
2.0480
2.8224
3.0720
Table 5. DAC System Clock Example (DAC Normal Speed Mode @Manual Setting Mode)
LRCKA/C
fs
MCLKA/C (MHz)
BICKA/C (MHz)
64fs
128fs
192fs
256fs
384fs
88.2kHz
96.0kHz
11.2896
12.2880
16.9344
18.4320
22.5792
24.5760
33.8688
36.8640
5.6448
6.1440
Table 6. DAC System Clock Example (DAC Double Speed Mode @Manual Setting Mode)
LRCKA/C
fs
MCLKA/C (MHz)
BICKA/C (MHz)
64fs
128fs
192fs
256fs
384fs
176.4kHz
192.0kHz
22.5792
24.5760
33.8688
36.8640
-
-
-
-
11.2896
12.2880
Table 7. DAC system clock example (DAC Quad Speed Mode @Manual Setting Mode)
MS1106-E-00
2009/08
- 20 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
