[AK4685]
■ ADC Clock Control
The integrated ADC of the AK4685 operates by the clock from MCB/XTI pin.
In master mode (MSB pin = “H”), the CKS11-0 bits select the clock frequency (Table 2). The ADC is in power-down
mode until MCB is supplied.
CKSB1
CKSB0
Clock Speed
256fs
0
0
1
1
0
1
0
1
(default)
384fs
512fs
768fs
Table 2. PORT1 Master Clock Control (ADC Master Mode)
In slave mode (MSB pin = “L”), the master clock (MCB) must be synchronized with LRCKB but the phase is not critical.
After exiting reset state when power-up the device or other situations (PDN pin = “H”), the ADC is in power-down mode
until MCB is input.
LRCKB
fs
MCB (MHz)
Sampling
Speed
128fs
192fs
256fs
384fs
512fs
768fs
-
-
-
-
-
-
8.1920
11.2896
12.2880
12.2880
16.9344
18.4320
16.3840
22.5792
24.5760
24.5760
33.8688
36.8640
32.0kHz
44.1kHz
48.0kHz
Normal
Table 3. System Clock Example (ADC Slave Mode)
MS1106-E-00
2009/08
- 19 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
