[AK4679]
■ Register Map (DSP block)
The DSP block control register settings are executed through a microcontroller interface. All registers below are
initialized by the power down (PDNE pin = “L”). To ensure control register settings, this power-down (PDNE pin= “L”)
must always be made when power up the AK4679.
Control register settings should be made during DSP reset (DSPRSTN bit = “0”).
Name
D7
0
D6
0
D5
0
D4
SOCFG
0
D3
0
D2
0
D1
0
D0
PCONT0
PCONT1
PWSW
MRSTN
0
0
0
0
0
0
Name
D7
D6
D5
D4
D3
D2
D1
0
D0
CONT0
CONT1
FSD[3]
FSD[2]
FSD[1]
FSD[0]
DIFD[0]
0
0
0
0
LAW[1]
LAW[0]
DIFD[1]
BCKPD
TESTB
WDTN
TESTA
BANK[0
CONT2
CONT3
BANK[3] BANK[2] BANK[1]
LOCKE
CRCE
0
EFEN
]
POMOD
DRAD[1
]
WAVP1[0
]
DRMS[1] DRMS[0]
E
DRAD[0]
WAVP1[1]
CONT4
CONT5
LPDO4
OUT4N
LPDO3
OUT3N
LPDO2
OUT2N
LPDO1
OUT1N
SELDO4
0
SELDO3
0
PT2N
0
SELPT
STRDY
DSPRST
N
CONT6
0
0
DLRDY
0
0
0
0
CONT7
CONT8
SYDET
TESTC
CGLK
0
0
0
0
0
0
0
0
0
0
0
0
0
Note 83. The bits defined as 0 must set a “0” value.
Note 84. Default value is the value after power-down release.
MS1402-E-06
2013/02
- 183 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
