[AK4679]
D0
Addr Register Name
80H DVLC Filter Select
R/W
D7
DLLPF1
R/W
D6
DLLPF0
R/W
D5
D4
D3
D2
D1
DMHPF1 DMHPF0 DMLPF1 DMLPF0 DHHPF1 DHHPF0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Default
0
0
DHHPF1-0: DVLC High Frequency Range HPF Coefficient Setting Enable (Table 58)
00: Disable (default)
01: 1st order HPF
10: 2nd order HPF
11: N/A
When DHHPF1-0 bits are “01” or “10”, the settings of DHHA13-0 and DHHB13-0 bits are enabled. When
DHHPF1-0 bits are “00”, HPF block outputs “0” data.
DMLPF1-0: DVLC Middle Frequency Range LPF Coefficient Setting Enable (Table 54)
00: Disable (default)
01: 1st order LPF
10: 2nd order LPF
11: N/A
When DMLPF1-0 bits are “01” or “10”, the settings of DMLA13-0 and DMLB13-0 bits are enabled. When
DMLPF1-0 bits are “00”, LPF block of DVLC middle frequency range is through (0dB).
DMHPF1-0: DVLC Middle Frequency Range HPF Coefficient Setting Enable (Table 53)
00: Disable (default)
01: 1st order HPF
10: 2nd order HPF
11: N/A
When DMHPF1-0 bits are “01” or “10”, the settings of DMHA13-0 and DMHB13-0 bits are enabled. When
DMHPF1-0 bits are “00”, HPF block of DVLC middle frequency range is through (0dB).
DLLPF1-0: DVLC Low Frequency Range LPF Coefficient Setting Enable (Table 49)
00: Disable (default)
01: 1st order LPF
10: 2nd order LPF
11: N/A
When DLLPF1-0 bits are “01” or “10”, the settings of DLLA13-0 and DLLB13-0 bits are enabled. When
DLLPF1-0 bits are “00”, LPF block outputs “0” data.
Addr Register Name
81H DVLC Mode Control
R/W
D7
D6
D5
D4
D3
D2
D1
DAF1
R/W
1
D0
DAF0
R/W
1
DVRGAIN2 DVRGAIN1 DVRGAIN0 DVLMAT2 DVLMAT1 DVLMAT0
R/W
0
R/W
1
R/W
1
R/W
0
R/W
1
R/W
1
Default
DAF1-0: Moving Average Parameter Setting for DVLC (Table 62)
Default: “11” (Default: 2048/fs)
DVLMAT2-0: DVLC ATT Speed Setting (Table 63)
Default: “011”
DVRGAIN2-0: DVLC Recovery Speed Setting (Table 64)
Default: “011”
MS1402-E-06
2013/02
- 180 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
