[AK4675]
■ Timing Diagram (CODEC, SRC)
1/fCLK
VIH1
VIL1
MCKI
tCLKH
tCLKL
1/fs
50%DVDD
LRCK
tLRCKH
tLRCKL
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
tBCK
50%DVDD
BICK
tBCKH
tBCKL
dBCK = tBCKH / tBCK x 100
tBCKL / tBCK x 100
1/fMCK
MCKO
50%DVDD
tMCKL
dMCK = tMCKL x fMCK x 100
Figure 4. Clock Timing (PLL/EXT Master mode)
Note 77. MCKO is not available at EXT Master mode.
tLRCKH
LRCK
50%DVDD
tBCK
tDBF
dBCK
BICK
(BCKP = "0")
50%DVDD
50%DVDD
BICK
(BCKP = "1")
tBSD
SDTO
SDTI
50%DVDD
MSB
tSDS
tSDH
VIH1
VIL1
Figure 5. Audio Interface Timing (PLL/EXT Master mode, DSP mode, MSBS = “0”)
MS0963-E-00
2008/05
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