[AK4675]
1/fCLK
VIH1
VIL1
MCKI
LRCK
tCLKH
tCLKL
1/fs
VIH1
VIL1
tLRCKH
tBCK
tLRCKL
Duty = tLRCKH x fs x 100
= tLRCKL x fs x 100
VIH1
VIL1
BICK
tBCKH
tBCKL
tMCKL
fMCK
50%DVDD
MCKO
dMCK = tMCKL x fMCK x 100
Figure 10. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin, Except DSP mode)
tLRCKH
VIH1
LRCK
VIL1
tLRB
VIH1
BICK
VIL1
(BCKP = "0")
VIH1
BICK
(BCKP = "1")
VIL1
tBSD
SDTO
50%DVDD
MSB
tSDH
tSDS
VIH1
VIL1
SDTI
MSB
Figure 11. Audio Interface Timing (PLL Slave mode, DSP mode; MSBS = “0”)
MS0963-E-00
2008/05
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