[AK4675]
The AK4675 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4675
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the
write cycle after the first data byte is transferred. After receiving each data packet the internal 6-bit address counter is
incremented by one, and the next data is automatically taken into the next address. In case of CODEC & SRC blocks, if
the address exceeds 5AH prior to generating stop condition, the address counter will “roll over” to 00H and the previous
data will be overwritten. In case of HP/SPK-Amp blocks, if the address exceeds 12H prior to generating stop condition,
the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only change when the clock signal on the SCL line is LOW (Figure 113) except for the START and STOP
conditions.
S
S
T
O
P
T
A
R
T
R/W="0"
Slave
Address
Sub
Address(n)
S
Data(n)
Data(n+1)
Data(n+x)
P
SDA
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 104. Data Transfer Sequence at the I2C-Bus Mode
CODEC
AMP
0
0
0
0
1
1
0
0
0
0
1
1
0
1
R/W
R/W
Figure 105. The First Byte
0
A6
D6
A5
A4
A3
A2
D2
A1
A0
D0
Figure 106. The Second Byte
D7
D5
D4
D3
D1
Figure 107. Byte Structure after The Second Byte
MS0963-E-00
2008/05
- 137 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
