[AK4646]
LRCK
0
1
2
3
9 10 11 12 13 14 15 0
1
2
3
9 10 11 12 13 14 15 0 1
BICK(32fs)
SDTO(o)
0 15 14
0 15 14
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0 15 14
0 15 14
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
SDTI(i)
0
1
2
3
15 16 17 18
31 0
1
2
3
15 16 17 18
31 0 1
BICK(64fs)
SDTO(o)
15 14
15 14
2
2
1
1
0
0
15 14
15 14
2
2
1
1
0
0
Don't Care
Don't Care
SDTI(i)
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 20. Mode 3 Timing
■ Mono/Stereo Mode
PMADL and PMADR bits set mono/stereo ADC operation.
When changing ADC operation, PMADL and PMADR bits should be set “0” at first.
PMADL bit
PMADR bit
ADC Lch data
All “0”
Rch Input Signal
Lch Input Signal
Lch Input Signal
ADC Rch data
All “0”
Rch Input Signal
Lch Input Signal
Rch Input Signal
0
0
1
1
0
1
0
1
(default)
Table 17. Mono/Stereo ADC operation
MS0557-E-05
2011/01
- 29 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
