ASAHI KASEI
[AK4645]
PLL Mode (AIN3 bit = “0”, PMPLL bit = “1”)
When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the
PLL3-0 and FS3-0 bits. The PLL lock time is shown in Table 5, whenever the AK4645 is supplied to a stable clocks after
PLL is powered-up (PMPLL bit = “0” → “1”) or sampling frequency changes. When AIN3 bit = “1”, the PLL is not
available.
1) Setting of PLL Mode
R and C of
VCOC pin
PLL Lock
Time
(max)
PLL3 PLL2 PLL1 PLL0 PLL Reference
Input
Frequency
Mode
bit
bit
bit
bit
Clock Input Pin
C[F]
R[Ω]
6.8k
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
0
2
0
0
0
0
0
1
0
0
LRCK pin
BICK pin
1fs
32fs
220n
4.7n
10n
160ms
2ms
4ms
2ms
4ms
40ms
40ms
40ms
40ms
40ms
40ms
40ms
60ms
60ms
Default
3
0
0
1
1
BICK pin
64fs
4.7n
10n
4
5
6
7
8
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
1
1
0
0
0
1
1
0
1
0
1
0
0
1
0
1
MCKI pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
N/A
11.2896MHz
12.288MHz
12MHz
4.7n
4.7n
4.7n
4.7n
4.7n
10n
24MHz
19.2MHz
13.5MHz
27MHz
13MHz
26MHz
12
13
14
15
Others
10n
220n
220n
Others
Table 5. Setting of PLL Mode (*fs: Sampling Frequency)
2) Setting of sampling frequency in PLL Mode
When PLL reference clock input is MCKI pin, the sampling frequency is selected by FS3-0 bits as defined in Table 6.
Mode
FS3 bit
FS2 bit
FS1 bit
FS0 bit
Sampling Frequency
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
8kHz
12kHz
16kHz
24kHz
7.35kHz
11.025kHz
14.7kHz
22.05kHz
32kHz
Default
10
11
14
15
Others
48kHz
29.4kHz
44.1kHz
N/A
Others
Table 6. Setting of Sampling Frequency at PMPLL bit = “1” (Reference Clock = MCKI pin)
MS0543-E-00
2006/09
- 25 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
