ASAHI KASEI
[AK4644]
Stereo Line Output (LOUT/ROUT pins)
When DACL bit is “1”, Lch/Rch signal of DAC is output from the LOUT/ROUT pins which is single-ended. When
DACL bit is “0”, output signal is muted and LOUT/ROUT pins output VCOM voltage. The load impedance is 10kΩ
(min.). When the PMLO=LOPS bits = “0”, the stereo line output enters power-down mode and the output is pulled-down
to AVSS by 100kΩ(typ). When the LOPS bit is “1”, stereo line output enters power-save mode. Pop noise at
power-up/down can be reduced by changing PMLO bit at LOPS bit = “1”. In this case, output signal line should be
pulled-down to AVSS by 20kΩ after AC coupled as Figure 45. Rise/Fall time is 300ms(max) at C=1µF and
AVDD=3.3V. When PMLO=LOPS bits = “1”, stereo line output is in normal operation.
LOVL bit set the gain of stereo line output.
“DACL”
“LOVL”
LOUT pin
ROUT pin
DAC
Figure 44. Stereo Line Output
LOPS
0
PMLO
Mode
LOUT/ROUT pin
Pull-down to AVSS
Normal Operation
Fall down to AVSS
Rise up to VCOM
0
1
0
1
Power-down
Normal Operation
Power-save
Default
1
Power-save
Table 47. Stereo Line Output Mode Select (x: Don’t care)
LOVL
Gain
0dB
+2dB
Output Voltage (typ)
0.6 x AVDD
0
1
Default
0.757 x AVDD
Table 48. Stereo Line Output Volume Setting
LOUT
ROUT
1µF
220Ω
20kΩ
Figure 45. External Circuit for Stereo Line Output (in case of using Pop Reduction Circuit)
MS0477-E-01
2006/10
- 54 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
