ASAHI KASEI
[AK4644]
PLL Master Mode (AIN3 bit = “0”, PMPLL bit = “1”, M/S bit = “1”)
When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 24MHz or 27MHz) is input to MCKI pin, the
MCKO, BICK and LRCK clocks are generated by an internal PLL circuit. The MCKO output frequency is selected by
PS1-0 bits (see Table 10) and the output is enabled by MCKO bit. The BICK output frequency is selected between 32fs or
64fs, by BCKO bit (see Table 11).
11.2896MHz, 12MHz, 12.288MHz
13.5MHz, 24MHz, 27MHz
AK4644
DSP or µP
MCKI
256fs/128fs/64fs/32fs
MCLK
BCLK
LRCK
MCKO
BICK
32fs, 64fs
1fs
LRCK
SDTI
SDTO
SDTI
SDTO
Figure 19. PLL Master Mode
Mode
PS1 bit
PS0 bit
MCKO pin
0
1
2
3
0
0
1
1
0
1
0
1
256fs
128fs
64fs
Default
32fs
Table 10. MCKO Output Frequency (PLL Mode, MCKO bit = “1”)
BICK Output
BCKO bit
Frequency
0
1
32fs
64fs
Default
Table 11. BICK Output Frequency at Master Mode
MS0477-E-01
2006/10
- 26 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
