ASAHI KASEI
[AK4644]
EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”)
The AK4644 becomes EXT Master Mode by setting PMPLL bit = “0” and M/S bit = “1”. Master clock is input from
MCKI pin, the internal PLL circuit is not operated. The clock required to operate is MCKI (256fs, 512fs or 1024fs). The
input frequency of MCKI is selected by FS1-0 bits (see Table 14).
MCKI Input
Frequency
Sampling Frequency
Range
Mode
FS3-2 bits
FS1 bit
FS0 bit
Don’t care
Don’t care
Don’t care
Don’t care
0
1
2
3
0
0
1
1
0
1
0
1
256fs
1024fs
256fs
512fs
Default
7.35kHz ∼ 48kHz
7.35kHz ∼ 13kHz
7.35kHz ∼ 48kHz
7.35kHz ∼ 26kHz
Table 14. MCKI Frequency at EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”)
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.
The out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output
through LOUT/ROUT pins at fs=8kHz is shown in Table 15.
S/N
MCKI
(fs=8kHz, 20kHzLPF + A-weighted)
256fs
512fs
1024fs
83dB
93dB
93dB
Table 15. Relationship between MCKI and S/N of LOUT/ROUT pins
MCKI should always be present whenever the ADC or DAC is in operation (PMADL bit = “1”, PMADR bit = “1” or
PMDAC bit = “1”). If MCKI is not provided, the AK4644 may draw excess current and it is not possible to operate
properly because utilizes dynamic refreshed logic internally. If MCKI is not present, the ADC and DAC should be in the
power-down mode (PMADL=PMADR=PMDAC bits = “0”).
AK4644
MCKO
DSP or µP
256fs, 512fs or 1024fs
MCKI
BICK
LRCK
MCLK
BCLK
LRCK
32fs or 64fs
1fs
SDTI
SDTO
SDTI
SDTO
Figure 24. EXT Master Mode
BICK Output
BCKO bit
Frequency
0
1
32fs
64fs
Default
Table 16. BICK Output Frequency at Master Mode
MS0477-E-01
2006/10
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AKM [ ASAHI KASEI MICROSYSTEMS ]
