ASAHI KASEI
[AK4644]
PLL Unlock State
1) PLL Master Mode (AIN3 bit = “0”; PMPLL bit = “1”, M/S bit = “1”)
In this mode, LRCK and BICK pins go to “L” and irregular frequency clock is output from MCKO pins at MCKO bit is
“1” before the PLL goes to lock state after PMPLL bit = “0” Æ “1”. If MCKO bit is “0”, MCKO pin goes to “L” (see
Table 8).
After the PLL is locked, a first period of LRCK and BICK may be invalid clock, but these clocks return to normal state
after a period of 1/fs.
When sampling frequency is changed, BICK and LRCK pins do not output irregular frequency clocks but go to “L” by
setting PMPLL bit to “0”.
MCKO pin
PLL State
BICK pin
LRCK pin
MCKO bit = “0”
“L” Output
MCKO bit = “1”
Invalid
After that PMPLL bit “0” Æ “1”
PLL Unlock (except above case)
PLL Lock
“L” Output
Invalid
See Table 11
“L” Output
Invalid
1fs Output
“L” Output
Invalid
“L” Output
See Table 10
Table 8. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
2) PLL Slave Mode (AIN3 bit = “0”, PMPLL bit = “1”, M/S bit = “0”)
In this mode, an invalid clock is output from MCKO pin before the PLL goes to lock state after PMPLL bit = “0” Æ “1”.
After that, the clock selected by Table 10 is output from MCKO pin when PLL is locked. ADC and DAC output invalid
data when the PLL is unlocked. For DAC, the output signal should be muted by writing “0” to DACL, DACH and DACS
bits.
MCKO pin
PLL State
MCKO bit = “0” MCKO bit = “1”
After that PMPLL bit “0” Æ “1”
PLL Unlock
PLL Lock
“L” Output
“L” Output
“L” Output
Invalid
Invalid
Output
Table 9. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
MS0477-E-01
2006/10
- 25 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
