[AK4627]
Addr Register Name
01H Control 2
Default
D7
0
0
D6
D5
D4
D3
0
0
D2
DFS0
0
D1
ACKS
0
D0
0
0
DFS1 LOOP1 LOOP0
0
0
0
ACKS: Master Clock Frequency Auto Setting Mode Enable
0: Disable, Manual Setting Mode
1: Enable, Auto Setting Mode
Master clock frequency is detected automatically at ACKS bit “1”. In this case, the settings of DFS bits
are ignored. When this bit is “0”, DFS0 and DFS1 bits set the sampling speed mode.
DFS1-0: Sampling speed mode (Table 1)
Register bit of DFS0 is ORed with DFS0 pin when the PS pin= “L”.
The settings of DFS bits are ignored at ACKS bit “1”.
LOOP1-0: Loopback mode enable
00: Normal (No loop back)
01: LIN1 → LOUT1, LOUT2, LOUT3
RIN1 → ROUT1, ROUT2, ROUT3
The digital ADC output is connected to the digital DAC input. In this mode, the input DAC data to
SDTI1-3 is ignored. In loopback mode, the actual audio format is forced to mode2 when the SDTO
audio format setting is for mode0/1/2, and the actual audio format is forced to mode3 when the setting
is for mode3. (Table 8)
10: SDTI1(L) → SDTI2(L), SDTI3(L)
SDTI1(R) → SDTI2(R), SDTI3(R)
In this mode the input DAC data to SDTI2-3 is ignored.
11: LIN2 → LOUT1, LOUT2, LOUT3
RIN2 → ROUT1, ROUT2, ROUT3
The digital ADC output is connected to the digital DAC input. In this mode, the input DAC data to
SDTI1-3 is ignored. In loopback mode, the actual audio format is forced to mode2 when the SDTO
audio format setting is for mode0/1/2, and the actual audio format is forced to mode3 when the setting
is for mode3. (Table 8)
MS1278-E-02
2012/03
- 37 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
