AK4545 参数 Datasheet PDF下载

[ASAHI KASEI]

n

Power On

[AK4545]

Note that AK4545 must be in cold reset at power on and RESET# must be low until master c rystal clock becomes

stable, or reset must be done once master clock is stable.

Vdd

RESET#

SDATA_OUT=”L”

SYNC=”L”

BIT_CLK

Initialize Registers

T

rst2clk

start up crystal oscillation

nCold

Reset Timing

Note that both SDATA_OUT and SYNC must be low at the rising edge of RESET# for cold reset.

The AK4545 initializes all registers including the Powerdown Control Registers, BIT-CLK is reactivated and each

analog output is in Hi-Z state except for PC Beep while RESET# pin is low.

The PC Beep is directly routed to L & R

line outputs when AK4545 is in Cold Reset.

At the rising edge of RESET #, the AK4545 starts the initialization of ADC and DAC , which takes 1028TS cycles.

After that, the AK4545 is ready for normal operation.

Status bit in the slot 0 is “0” (not ready) when the AK4545 is in RESET period ( “L”) or in initialization process.

After initialization cycles, the status bit goes to “1” (ready).

T

rst_low

RESET#

V

IL

SDATA_OUT=”L”

SYNC=”L”

BIT_CLK

T

rst2clk

MS0058-E-00

-8-

2000/11