[ASAHI KASEI]
[AK4545]
Slot
0
1
2
3
4
5
6
7
8
9
10
11
12
SYNC
SDATA
OUT
SPDIF Out SPDIF Out
Channel1 Channel2
TAG
TAG
Command Command PCM(dac) PCM(dac)
All
0
All
0
All
0
All
0
All
0
All
0
Address
Data
Left
Right
SDATA
IN
Status
Address
Status
Data
PCM(adc) PCM(adc)
Left Right
All
0
All
0
All
0
All
0
All
0
All
0
All
0
All
0
Tag Phase
Data Phase
48kHz
AC-link protocol identifies 13slots of data per frame. The frequency of sync is fixed to 48kHz. Only Slot 0, which is
the Tag phase, is 16bits, all other slots are 20bits in length. These slots are explained in later sections.
AC-link Audio Output Frame (SDATA_OUT)
a)Slot 0
SYNC
BIT_CLK
Valid
Frame
Slot7 Slot8 Slot9 Slot10 Slot11 Slot12
Slot14 Slot15
Slot1 Slot2 Slot3 Slot4 Slot5 Slot6
Slot13
Bit2
0
SDATA_OUT
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
Bit7 Bit6 Bit5 Bit4
0 0
0 1/0 1/0 0
Bit3
0
Bit1
0
Bit0
0
1/0 1/0 1/0 1/0 1/0 0
Slot 0
Slot 1
1 BIT_CLK delay
The AK4545 checks bit15 (valid frame bit). Note that when the valid frame bit is 1, at least one bit14-7 (slot 1-8)
must be valid, bit6-0 will be 0and should be ignored.
If bit15 is 0, the AK4545 ignores all following information in the frame.
The AK4545 then checks the validity of each bit in the TAG phase (slot 0).
Bit14-11,8,7 are valid bits for slot1-4,7,8.
If each bit is 0, the AK4545 ignores the slot indicated by 0. On the other hand, if each bit is 1, the slot is valid.
A new audio output frame begins with a low to high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. On the
immediately following falling edge of BIT_CLK, the AK4545 samples the assertion of SYNC. This falling edge marks the time when
both sides of AC-link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AC ’97 controller transitions
SDATA_OUT into the first bit position of slot 0 (Valid Frame bit). Each new bit position is presented to AC-link on a rising edge of
BIT_CLK, and subsequently sampled by the AK4545 on the following falling edge of BIT_CLK. This sequence ensures that data
transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned.
Data should be sent to the AC97 codec with MSB first through the SDATA_OUT.
The following table shows the relationship of bit14&13 and the Read/Write operation depending on codec ID
configuration.
Bit 15
Valid Frame
Bit 14: Slot1 Valid Bit
(Command Address)
Bit 13: Slot 2 Valid Bit
(Command Data)
Read/Write Operation of
AK4545
1
1
1
1
0
1
1
1
0
Read/Write(Normal Operation)
Ignore
Read: Normal Operation
Write: Ignore
1
0
0
Ignore
AK4545 Addressing: Slot0 Tag Bits
- 12 -
MS0058-E-00
2000/11
AKM [ ASAHI KASEI MICROSYSTEMS ]
