[ASAHI KASEI]
[AK4545]
nSignal Rise and Fall Times
(50pF external load : from 10% 90% of DVdd)
Trise_clk
BIT_CLK
Tfall_clk
Trise_din
SDATA_IN
Tfall_din
Trise_dout
SDATA_OUT
Tfall_dout
Trise_sync
SYNC
Tfall_sync
nAC-link Low Power Mode Timing
Slot 1
Slot 2
Ts2_pdwn
BIT_CLK
SDATA_OUT
Write to 0x26
Data PR4=1
Dont care
SDATA_IN
Thold
nActivate Test Mode
RESET#
VIH
VIH
SDATA_OUT
Tsetup2rst
HI-Z
SDATA_IN
BIT_CLK
Toff
Notes:1
1. All AC-link signals are normally low through the trailing edge of RESET#. Bringing SDATA_OUT high for the rising edge of
RESET# causes the AK4545 AC-link outputs to go high impedance which is suitable for ATE in circuit testing. Note that the
AK4545 enters in the ATE test mode regardless SYNC is high or low.
2. Once test modes have been entered, the only way to return to the normal operating state is to issue “cold reset” which issues
RESET# with both SYNC and SDATA_OUT low.
1 All the following sentences written with small italic font in this document quote the AC’ 97 component specification.
- 10 -
MS0058-E-00
2000/11
AKM [ ASAHI KASEI MICROSYSTEMS ]
