[ASAHI KASEI]
nWarm
Reset
[AK4544A]
The AK4544A initiates warm reset process by receiving a single pulse on the sync. The AK4544A clears PR4 bit and
PR5 bit in the Powerdown Control Register. However, warm reset does not influence PR0∼PR3 or PR6,7 bits in
Powerdown Control Register. Note that SYNC signal should synchronize with BIT_CLK after AK4544A starts to
output BIT_CLK clock. And if an external clock is used, external clocks should be supplied before issuing a sync
pulse for warm reset.
ADC and DAC require 1028TS for the initialization.
T
sync_high
SYNC
T
sync2clk
V
IH
BIT_CLK
Please refer to the appendix on the warm reset when the AK4544A is used under the multiple codec configuration.
nBIT_CLK
Timing
T
clk_high
BIT_CLK
T
clk_low
50%
nSYNC
Timing
T
sync_high
SYNC
T
sync_low
V
IH
V
IL
T
sync_period
nSetup
and Hold Timing
T
delay
BIT_CLK
T
setup
V
IH
V
IL
V
IH
V
IL
T
hold
SDATA_IN
SDATA_OUT
SYNC
V
IH
V
IL
<MS0026-E-00>
-9-
2000/04
AKM [ ASAHI KASEI MICROSYSTEMS ]
