[ASAHI KASEI]
[AK4544A]
Slot
0
1
2
3
4
5
6
7
8
9
10
11
12
SYNC
Codec ID1:Codec ID0=0:0 or 0:1
TAG Command Command PCM(dac) PCM(dac)
SDATA
OUT
All
“0”
All
“0”
All
”0”
All
“0”
All
“0”
All
“0”
All
“0”
All
“0”
Address
Codec ID1:Codec ID0=1:0
TAG Command Command
Data
Left
Right
All
“0”
All
“0”
All
“0”
All
“0”
PCM(dac) PCM(dac)
Left
All
“0”
All
“0”
All
“0”
All
“0”
Address Data
Right
Codec ID1:Codec ID0=1:1
TAG
TAG
Command Command
All
“0”
All
“0”
All
“0”
PCM(dac)
Left
All
”0”
All
“0”
PCM(dac)
Right
All
“0”
All
“0”
All
“0”
Address
Data
SDATA
IN
Status
Address
Status
Data
PCM(adc) PCM(adc)
Left Right
All
“0”
All
“0”
All
”0”
All
“0”
All
“0”
All
“0”
All
“0”
All
“0”
Tag Phase
Data Phase
48kHz
AC-link protocol identifies 13slots of data per frame. The frequency of sync is fixed to 48kHz. Only Slot 0, which is
the Tag phase, is 16bits, all other slots are 20bits in length. These slots are explained in later sections.
AC-link Audio Output Frame (SDATA_OUT)
a)Slot 0
Primary codec(CodecID1:CodecID0=0:0)
SYNC
BIT_CLK
Valid
Frame
Slot7 Slot8 Slot9 Slot10
Slot12
Slot1 Slot2 Slot3 Slot4 Slot5 Slot6
Slot11
SDATA_OUT
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9” Bit8
Bit7” Bit6” Bit5” Bit4
Bit3
“0”
Bit2
“0”
Bit1
“0”
Bit0
“0”
“0”
“0”
“1/0” “1/0” “1/0” “1/0” “1/0” “0”
Slot 0
“0” “0”
“0” “0”
Slot 1
1 BIT_CLK delay
Secondary codec (CodecID1:CodecID0 = 0:1 or 1:0 or 1:1)
SYNC
BIT_CLK
Valid
Frame
Slot7 Slot8 Slot9 Slot10
Slot12
Slot1 Slot2 Slot3 Slot4 Slot5 Slot6
Slot11
SDATA_OUT
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9” Bit8
Bit7” Bit6” Bit5” Bit4
“0” “0”
“1/0” “1/0” “1/0” “1/0”
Bit3
“0”
Bit2
“0”
Bit1
Bit0
“1/0” “1/0”
“1/0” “0”
“0” “1/0” “1/0” “0”
Slot 0
Slot 1
1 BIT_CLK delay
The AK4544A checks bit15 (valid frame bit). Note that when the valid frame bit is “1”, at least one bit14-6 (slot 1-9)
or bit1-0 must be valid, bit5-2 will be “0”and should be ignored.
If bit15 is “0”, the AK4544A ignores all following information in the frame.
The AK4544A then checks the validity of each bit in the TAG phase (slot 0).
If each bit is “0”, the AK4544A ignores the slot indicated by “0”. On the other hand, if each bit is “1”, the slot is valid.
All bits in slot10-12(bit5-3) are “0” and bit2 is also “0”.
The AK4544A monitors bit1 and 0, which are codec ID configuration bits used in multiple codec designs. These bits
are used to identify which codec the frame data is issued to.
<MS0026-E-00>
2000/04
- 13 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
