[ASAHI KASEI]
Switching Characteristics
Ta=25°C, AVdd=5.0V±5%, DVdd=3.3V±5% or 5V±5%, 50pF external load
Parameter
Symbol
Min
Master Clock Frequency Note)
Fmclk
-
If Crystal is not used.
45
AC link Interface Timing
Fbclk
BIT_CLK frequency
-
Tbclk
BIT_CLK clock Period(Tbclk=1/Fbclk)
36
Tclk_low
BIT_BLK low pulse width
36
Tclk_high
BIT_BLK low pulse width
-
Trise_clk
BIT_CLK rise time
-
Tfall_clk
BIT_CLK fall time
SYNC frequency
-
SYNC low pulse width
Tsync_low
-
SYNC high pulse width
SYNC rise time
SYNC fall time
Setup time(SYNC, SDATA_OUT)
Hold time(SYNC, SDATA_OUT)
SDATA_IN delay time from BIT_CLK
rising edge
SDATA_IN rise time
SDATA_IN fall time
SDATA_OUT rise time
SDATA_OUT fall time
Cold Rest
(SDATA_OUT=L, SYNC=L)
RESET# active low pulse width
RESET# inactive to BIT_CLK delay
Warm Rest Timing
SYNC active low pulse width
SYNC inactive to BIT_CLK delay
Tsync_high
Trise_sync
Tfall_sync
Tsetup
Thold
Tdelay
Trise_din
Tfall_din
Trise_dout
Tfall_dout
Trst_low
Trst2clk
Tsync_high
Tsync2clk
-
-
-
10
25
-
-
-
-
-
1.0
162.8
(2 cycle)
1.0
162.8
(2 cycle)
[AK4544A]
Typ
24.576
50
12.288
81.38
40.7
40.7
-
-
48
19.5
(240 cycle)
1.3
(16 cycle)
-
-
-
-
-
-
-
-
-
-
max
-
55
Units
MHz
%
MHz
ns
ns
ns
ns
ns
kHz
µs
(Tbclk)
µs
(Tbclk)
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
(Tbclk)
µs
(Tbclk)
ns
(Tbclk)
45
45
6
6
-
-
-
6
6
-
-
15
6
6
6
6
-
1.3
(16 cycle)
-
AC-link Low Power Mode Timing
End of Slot 2 to BIT_CLK, SDATA_IN
Ts2_pdwn
-
-
1.0
µs
Low
Activate Test Mode Timing
Setup to trailing edge of RESET#
Tsetup2rst
15.0
-
-
ns
Hold from RESET# rising edge
Thold2rst
100
-
-
ns
Rising edge of RESET# to Hi-Z
Toff
-
-
50
ns
Falling edge of RESET# to “L”
Tlow
-
-
50
ns
Note ) The use of a crystal is recommended. If master clock is supplied from controller (or if a external oscillator is
used), Master Clock should be input to XTAL_IN, meanwhile XTAL_OUT should be open.
<MS0026-E-00>
-7-
2000/04
AKM [ ASAHI KASEI MICROSYSTEMS ]
