[ASAHI KASEI]
The interface of touch screen controller block shares with audio control interface. (For the detail of read/write
sequence, please see "Figure 12. Audio/Touch Screen Control Interface Timing")
Touch Screen Control Register
D7
D6
D5
X
D4
X
D3
D3
D2
D2
D1
D1
D0
D0
Addr
07
Default
80
TSPD
PW
Touch Screen Control
Table 7. Touch Screen Control Register
D3:D0 Selection of Input Channel/Output Channel
Table 8 describes the relationship between D3:D0 bits and the states of TSX_TOP, TSX_BTM, TSY_TOP, TSY_BTM,
AIN, and VREF.
As TSX_TOP, TSX_BTM, TSY_TOP, and TSY_BTM can output one of the three voltage level, VA, AGND, and Hi-Z
by the combination of D3:D0 bits, touch screen control block is very flexible. For example, there are two ways to
measure the x-axis spot as No.1 configuration or No.2 configuration in Table 8.
Touch Screen
Control Register(07h)
The State of Touch Screen
Terminals
Analog
Input
AIN
VREF
Input
VREF
No
.
0
1
2
3
4
5
6
7
D7
D6
D3 D2 D1 D0 TSX_
TSX_
BTM
AGND
VA
OPEN
OPEN
OPEN
OPEN
AGND
OPEN
OPEN
OPEN
TSY_
TOP
OPEN
OPEN
VA
AGND
AGND
OPEN
OPEN
AGND
OPEN
OPEN
TSY_
BTM
OPEN
OPEN
AGND
VA
OPEN
OPEN
OPEN
AGND
OPEN
OPEN
VA
Note
(TSPD)
(PW)
TOP
VA
TSY_TOP
TSY_TOP
TSX_TOP
TSX_TOP
X
VA
VA
VA
VA
VA
VA
VA
VA
X-axis Measurement
X-axis Measurement
Y-axis Measurement
Y-axis Measurement
Discharge
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
X
X
X
0
0
1
1
0
0
1
1
X
X
X
0
1
0
1
0
1
0
1
0
1
0
AGND
OPEN
OPEN
AGND
OPEN
AGND
OPEN
OPEN
OPEN
X
X
X
Discharge
Discharge
BTI_1
BTI_2
BTI_1
TPVREFIN Battery Measurement
TPVREFIN Battery Measurement
TPVREFIN Pen Waiting &
Battery Measurement
TPVREFIN Pen Waiting &
Battery Measurement
8
9
10
OPEN AGND_R OPEN
OPEN AGND_R OPEN
OPEN AGND_R OPEN
VA
VA
BTI_2
11
12
13
0
1
1
1
1
0
1
X
X
X
X
X
X
X
X
1
X
X
X
X
X
Pen Waiting &
Power Down State
Power Down State
(Default)
OPEN
OPEN
OPEN
OPEN
X
VA
AGND
OPEN
Power Supply Voltage
Analog Ground
Hi-Z state
BTI_1,BTI_2
TPVREFIN
AGND_R
Measurement of Buttery Voltage
External Reference Voltage
TSX_BTM is connected to AGND through internal resistor.
Table 8. The relationship between input/output channel and D3:D0 bits
<Revision 0.9a>
29
July 00
AKM [ ASAHI KASEI MICROSYSTEMS ]
