[ASAHI KASEI]
Parameter
Audio
Symbol
min
Note1)
Typ
max
Units
from Power stable to PDBÇ
from PDB Ç to RESETBÇ
from RESETBÈ to PDBÈ
tPDD
tRSTD
0
0
0
ms
ms
Note 2)
Note 2)
4
Note 3)
Clear Power-down mode
from MCLK input to 16CCLKÈ
from 16CCLKÈ to LRCKÇ
Initialize Time Note 4)
t1
t2
1
tMCLK
tMCLK
1
A/D (MSEL=”L”)
A/D (MSEL=”H”)
D/A
tIAD
tIAD
tIDA
260
516
2
Ts
Ts
Ts
Power Down
from 16CCLKÈ to LRCK stop (”L”)
from 16CCLKÈ to SCLK Stop (”L”)
from 16CCLKÈ to MCLK stop
t3
t3
t4
10
10
ns
ns
tMCLK
0
tMCLK= 1/fMCLK
Ts=1/fs
Note 1) VA, VD pins and PDB pins can be powered at the same time. However, PDB should NOT be powered before VA and VD.
Otherwise, the device may be damaged, and the device may be destroyed at worst case.
Note 2) PDB pin and RESETB can be set to "H" at the same time. But note that the pop noise occurs at the transition of PDB. Keeping
PDB pin high is suggested for preventing pop noise while the device is powered. Power management can be controlled by RESETB
pin.
Note 3) The time in which VCOM settles to 95% of VDD with 4.7 µF and 0.1 µF capacitors.
Note 4) ADC initialization cycle, which takes 516@ MSEL="H", or 260Ts@TSEL-"L", starts after exiting ADC's power-down mode.
In this cycle, the write to the register is possible, but the device disables AGC function. The device enables AGC automatically after this
initialization cycle completes. DAC initialization cycle is 2Ts.
<Revision 0.9a>
27
July 00
AKM [ ASAHI KASEI MICROSYSTEMS ]
