[ASAHI KASEI]
System Clock and Power-up Timing
MCLK, the master clock, must be present while ADC or/and DAC is under normal operation. Otherwise, excessive current may result
from abnormal operation of internal dynamic logic. Clock should be stopped after power-down state.
PDB pin must be set to "H" first, and then, RESETB pin must be set to "H". After RESETB pin is cleared, ADC, and DAC are still in
power-down mode. In order to activate ADC and/or DAC, write DALPD bit, DARPD bit and/or ADPD bit to "0" through A/T I/F.
Note that MCLK must be present when ADC and/or DAC is under normal operation.
MCLK should be present when all registers except for MSEL bit should be accessed. MSEL bit should be updated without MCLK
input.
MCLK can be stopped after RESETB = "L" or all of ADPD, DALPD, and DARPD are set to "1".
Power
Supply
PDB
RESETB
All Block
Powerdown
ADC and DAC are
normal operation
Internal
State
Registers are default value
A/D, D/A is powered down
Powerdown
except for VCOM
LRCK
MCLK
CS
CCLK
ADPD=” 0”
DALPD=” 0”
DARPD=” 0”
CDTI
MSEL=” 1”
in case that fs is more than 22.05kHz
Figure 14. Power-up Timing (1)
<Revision 0.9a>
25
July 00
AKM [ ASAHI KASEI MICROSYSTEMS ]
