ASAHI KASEI
[AK4522]
SWITCHING CHARACTERISTICS
(Ta=25°C; VA=4.5 ∼ 5.5V, VD=2.7 ∼ 5.5V; CL=20pF)
Parameter
Symbol
min
typ
max
Units
Master Clock Timing
External Clock
256fs:
Pulse Width Low
Pulse Width High
384fs:
fCLK
tCLKL
tCLKH
fCLK
4.096
27
12.288
MHz
ns
27
ns
6.144
20
18.432
24.576
MHz
ns
Pulse Width Low
Pulse Width High
tCLKL
tCLKH
fCLK
20
ns
512fs:
8.192
15
MHz
ns
Pulse Width Low
Pulse Width High
tCLKL
tCLKH
15
ns
LRCK
Frequency
fsn
dfs
16
45
44.1
48
55
kHz
%
Duty Cycle
Serial Interface Timing
Slave mode
SCLK Period
tSCK
tSCKL
tSCKH
tLRS
160
65
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK Pulse Width Low
Pulse Width High
65
LRCK Edge to SCLK “↑”
SCLK “↑” to LRCK Edge
LRCK to SDTO(MSB)
SCLK “↓” to SDTO
SDTI Hold Time
(Note 13)
(Note 13)
45
tSLR
45
tLRM
tSSD
40
50
tSDH
tSDS
40
25
SDTI Setup Time
Reset Timing
PD Pulse Width
tPD
150
ns
PD “↑” to SDTO valid
(Note 14)
tPDV
516
1/fs
Note 13. SCLK rising edge must not occur at the same time as LRCK edge.
14. These cycles are the number of LRCK rising from PD rising.
The AK4522 can be reset by bringing PD “L”.
M0020-E-02
2012/01
- 7 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
